Dublin, March 20, 2017 (GLOBE NEWSWIRE) -- Research and Markets has announced the addition of the "STMicroelectronics Time of Flight Proximity Sensor in the Apple iPhone 7 Plus" report to their offering. Located in the front above the main speaker, the proximity sensor is packaged using optical LGA. The iPhone 7 Plus features the smallest Time of Flight sensor provided by STMicroelectronics. As always, Apple has ordered a custom version of the device. Compared to STMicroelectronics's portfolio, the custom device is two time smaller (2.80 x 2.40 mm) than the actual proximity sensor proposes by the firm. The sensor is based on FlighSenseTM technology that featured an illumination device which is a Vertical-Cavity Surface-Emitting Laser (VCSEL) and a collector which is based on the Single Photon Avalanche Diode (SPAD) developed by STMicroelectronics. To provide such device, STMicroelectronics has made some improvement on the SPADs and the VCSEL from the actual devices that are studied and detailed in the report. The report featured also a function and a field-of-view comparison with the VL53L0X and VL6180X. Key Topics Covered: Overview /Introduction - STMicroelectronics Company Profile & Time of Flight technology - Apple iPhone 7 Plus Teardown Physical Analysis - Physical Analysis Methodology - Package - View and Dimensions - Package Opening & Wire Bonding Process - Package Cross-Section: Adhesives, PCB, Filters, FOV - VCSEL Die - View & Dimensions - Wire Bonding, Cavity - Cross-Section - Process Characteristics - ASIC Die - View, Dimensions & Marking - Die Overview: Active Area, SPADs technology - Die Delayering, Main Blocks ID & Process - Cross-Section: Metal Layers, SPADs - Process Characteristics Physical Comparison with VL53L0X and VL6180X - Package, Functions, FOV, Optical Blocking Package, ASIC & VCSEL, SPADs Manufacturing Process Flow - Overview - ASIC Front-End Process - VCSEL Front-End Process - ASIC Wafer Fabrication Unit - VCSEL Wafer Fabrication Unit - Packaging Process Flow - Final Assembly Unit Cost Analysis - Cost Analysis Synthesis - The Main Steps Used in the Economic Analysis - Yield Hypotheses - ASIC & VCSEL Die Cost - Front-End Cost - Back-End: Tests and Dicing - Wafer and Die Cost - Component - Packaging Cost - Packaging Cost per Process Steps - Component Cost Estimated Price Analysis For more information about this report visit http://www.researchandmarkets.com/research/6c...lectronics
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