Keysight Technologies Launches Chiplet PHY Designer 2025
Keysight Technologies, Inc. (NYSE: KEYS) has unveiled its latest innovation, the Chiplet PHY Designer 2025, aimed at advancing high-speed digital chiplet designs specifically tailored for AI and data center applications. This new solution enhances simulation capabilities by supporting the Universal Chiplet Interconnect Express™ (UCIe™) 2.0 standard and the Open Computer Project Bunch of Wires (BoW) standard. The Chiplet PHY Designer serves as an advanced solution for system-level chiplet design, providing essential tools for pre-silicon validation and easing the design process leading up to tapeout.
Key Reasons to Consider Chiplet PHY Designer 2025
As the complexity of AI and data center chips increases, ensuring a reliable connection between chiplets is paramount for optimal performance. The adoption of open, emerging standards like UCIe and BoW facilitates this connectivity, defining interconnects within advanced 2.5D and 3D packaging. By verifying their designs against these standards, chip designers can become part of a larger ecosystem aimed at enhancing chiplet interoperability, thus lowering both costs and risks associated with semiconductor development.
Notable Features of Chiplet PHY Designer 2025
1. Ensures Interoperability
The software verifies that designs comply with UCIe 2.0 and BoW standards, allowing for seamless integration within various advanced packaging environments.
2. Accelerates Time-to-Market
Chiplet PHY Designer 2025 automates tasks such as simulation and compliance testing setup, which includes critical aspects like Voltage Transfer Function (VTF), simplifying the overall workflow of chiplet design.
3. Improves Design Accuracy
By focusing on crucial metrics such as signal integrity, bit error rates (BER), and crosstalk analysis, this tool minimizes the chances of costly errors during silicon production.
4. Optimizes Clocking Designs
It supports advanced clocking scheme analysis allowing for precise synchronization necessary for high-speed interconnects, which is vital for enhancing overall performance.
Insights from Industry Leaders
According to Hee-Soo Lee, High-Speed Digital Segment Lead at Keysight EDA, "Chiplet PHY Designer launched as the industry’s first pre-silicon validation tool. It provides in-depth modeling and simulation capabilities, enabling designers to accurately verify compliance with specifications prior to tapeout. The latest iteration reflects evolving standards like UCIe 2.0 and BoW while integrating new features such as the quarter-rate data rate and systematic crosstalk analysis. Users of the Chiplet PHY Designer save time and avoid rework, which is crucial for ensuring design performance before moving into production. Early adopters, including Alphawave Semi, have confirmed that the Chiplet PHY Designer facilitates seamless operation and interoperability for their chiplet solutions."
Demonstration of Chiplet PHY Designer at DesignCon
For those interested in learning more, Keysight will showcase the Chiplet PHY Designer at the upcoming DesignCon event. Attendees can find Keysight's booth, #1039, at the Santa Clara Convention Center between January 29 and 30 in 2025, providing an excellent opportunity to see the tool in action.
About Keysight Technologies
Keysight Technologies (NYSE: KEYS) empowers innovators globally by delivering advanced design, emulation, and testing solutions. As an S&P 500 company, it supports engineers in expediting their development processes while minimizing risk. Keysight strives to connect and secure the world through innovation in various industries, including communications, industrial automation, aerospace and defense, automotive, semiconductor, and general electronics markets. Explore more about Keysight and their initiatives through the Keysight Newsroom and official website.
Frequently Asked Questions
1. What is Chiplet PHY Designer 2025?
Chiplet PHY Designer 2025 is a design tool by Keysight aimed at enhancing high-speed digital chiplet design for AI and data center applications.
2. How does it ensure interoperability?
The tool verifies designs against UCIe 2.0 and BoW standards, which helps in seamless integration of chiplets within advanced packaging environments.
3. What are the key features of the Chiplet PHY Designer 2025?
Key features include ensuring interoperability, accelerating time-to-market, improving design accuracy, and optimizing clocking designs.
4. Where can I see Chiplet PHY Designer in action?
Keysight will demonstrate Chiplet PHY Designer at the DesignCon event, at booth #1039, from January 29 to 30, 2025.
5. How does Chiplet PHY Designer benefit engineers?
It saves engineers time and helps avoid costly rework by allowing them to validate designs before manufacturing, ensuring they meet performance standards.
