Arteris Enhances AI Semiconductor Design with NoC Tiling

Revolutionizing AI with Network-on-Chip Tiling

Highlights:

• Scalable Performance: Expanded network-on-chip tiling supported by mesh topology capabilities enables designs with AI to easily scale by more than 10 times without altering the fundamental architecture to address AI's increasing demand for speed and powerful computing.
• Power Efficiency: The dynamic shutdown of network-on-chip tiles can reduce energy consumption by an average of 20%, crucial for developing sustainable AI solutions with lower operational costs.
• Design Reusability: Utilizing pre-tested network-on-chip tiles can cut integration time for system-on-chip (SoC) designs by up to 50%, promoting quicker market entry for AI innovations.

Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP, is on the frontline of semiconductor advancement. It recently unveiled an innovative upgrade to its network-on-chip (NoC) IP products, introducing tiling capabilities and extensive mesh topology support. This advancement is essential for propelling Artificial Intelligence (AI) and Machine Learning (ML) computations in SoC designs, enabling teams to boost performance by over 10 times while also meeting ambitious project timelines and goals regarding power, performance, and area (PPA).

The Evolution of Network-on-Chip Tiling

Network-on-chip tiling has become a vital innovation trend in SoC design. By leveraging proven NoC IP, this evolutionary method condenses design time, accelerates validation processes, and diminishes design risks. SoC architects can create flexible and scalable designs by replicating soft tiles across the architecture. Each soft tile functions as a self-sufficient component, facilitating swift integration, verification, and optimization.

Combining Tiling with Mesh Topologies

The combination of tiling and mesh topologies in Arteris' flagship NoC products, FlexNoC and Ncore, represents a game-changer for the increasing need for AI-capable systems in most SoCs. As the scale of AI systems expands, this innovative approach allows additional soft tiles to be integrated without necessitating a complete redesign. Consequently, the overall time for XPU subsystem design and SoC connectivity execution can decline by up to 50% compared to traditional, non-tiled methods.

Modular Design and Enhanced Performance

The initial version of NoC tiling organizes Network Interface Units (NIUs) into modular and repeatable blocks, greatly enhancing scalability, efficiency, and reliability within SoC designs. These designs support drastically increasing AI workloads for various applications including Vision, Machine Learning (ML), Deep Learning (DL), Natural Language Processing (NLP), and Generative AI (GAI), catering to both training and inference tasks.

Client Testimonials and Future Prospects

According to Srivi Dhruvanarayan, VP of hardware engineering at SiMa.ai, "Thanks to Arteris’ highly scalable and flexible mesh-based NoC IP, our SoC team has proficiently handled larger AI data volumes and complex algorithms. The close collaboration with Arteris has enabled us to define an Arm-based, multi-modal, software-centric edge AI platform that accommodates diverse models from CNNs to multimodal GenAI, thus enhancing scalable performance per watt."

K. Charles Janac, President and CEO of Arteris, stated, "Our continuous innovation reflects our commitment to advancing SoC design technology. Our clients, developing cutting-edge AI-powered SoCs, are now better positioned to develop larger, more intricate AI systems more effectively, all while adhering to their PPA targets."

Early Access for Enhanced NoC IP Products

The latest versions of FlexNoC and Ncore NoC IP, which incorporate advanced AI support through tiling and expanded mesh topology capabilities, are now available to select early-access customers and partners.

About Arteris

Arteris specializes in providing system IP that accelerates the design of system-on-chip (SoC) infrastructures across the electronics landscape. The network-on-chip interconnect IP and SoC integration automation technologies developed by Arteris significantly enhance product performance while minimizing power consumption and expediting time to market. Their focus ensures improved SoC economics, enabling clients to concentrate on what innovations lie ahead.

Frequently Asked Questions

What is network-on-chip tiling?

Network-on-chip tiling is an innovative design approach that uses modular, repeatable components within SoCs to enhance scalability and efficiency, particularly for AI applications.

How does Arteris enhance power efficiency?

Arteris' network-on-chip tiles can be dynamically turned off to reduce overall energy consumption by an average of 20%, supporting sustainable technology development.

What are the benefits of using modular designs?

Modular designs, such as those provided by Arteris, support faster integration and optimization, cutting design time significantly and improving reliability.

What industries benefit from the new NoC capabilities?

Industries focused on AI, such as automotive, healthcare, and consumer electronics, can leverage Arteris' enhanced NoC capabilities for sophisticated AI workloads.

Where can I find more information about Arteris's offerings?

For additional details about Arteris and its innovative solutions, you can visit their website at arteris.com.

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