Tower Semiconductor Introduces Groundbreaking CPO Foundry Technology
Leveraging extensive experience in stacked BSI sensor production, Tower Semiconductor is proud to present its cutting-edge advancements in 3D-IC technology. This innovation is set to enhance the integration of Silicon Photonics (SiPho) and Electronic IC (EIC) processes, particularly for applications like Co-Packaged Optics (CPO). The new technology also enjoys robust support from Cadence design tools, which will facilitate seamless operation on the stacked platform.
Advancements in Wafer Bonding Technology
In a notable expansion, Tower Semiconductor has adapted its mature 300mm wafer bonding technology, which has a successful legacy with stacked BSI image sensors. This enhancement is crucial for achieving heterogeneous 3D-IC integration across its prominent Silicon Photonics and SiGe BiCMOS processes. Not only does this technology advance wafer-scale 3D integration, but it also utilizes various Process Design Kits (PDKs) to cater to a growing market need for high-performance, compact systems suitable for data center applications.
Innovative 3D-IC Design Capability
By building on years of high-volume production with both 200mm and 300mm wafers, Tower’s advanced wafer bonding technology allows for the stacking of wafers—essentially combining SiPho (PIC - Photonic IC) and SiGe (EIC - Electronic IC) to forge fully integrated 3D-ICs at a wafer scale. This capability means that application-specific functions can converge from different process technologies into a single, high-density chip, maximizing performance and functionality while minimizing space usage.
Customer-Centric Enhancements
“Our long-standing experience in high-volume wafer stacking for CIS technologies has paved the way for this next generation of 3D integration,” stated Dr. Marco Racanelli, President of Tower Semiconductor. He expressed enthusiasm about the advancements in their 300mm wafer bonding processes, noting they are now compatible with multiple wafer technologies on a single 3D-IC. This means Tower Semiconductor's customers can reach new heights in performance, functionality, and integration density, especially vital for CPO applications.
Collaborative Efforts with Cadence Design Systems
To further enhance the design processes, Tower Semiconductor has partnered with Cadence Design Systems, extending the capabilities of their Virtuoso Studio integrated design flow. This layout allows for co-simulation and co-verification across various process technologies within a unified design environment—an invaluable resource for designers. It streamlines the operational flow in complex multi-technology die projects, significantly boosting the likelihood of first-pass success.
The Impact of Tower Semiconductor's Innovations
Dr. Samir Chaudhry, Vice President of Customer Design Enablement at Tower, shared insights on the collaboration. “Together, Tower Semiconductor and Cadence have crafted a design flow that empowers designers to not only lay out and verify their connections but also conduct comprehensive simulations of 3D-IC and wafer-bonded chips from multiple technology platforms—all under a single Cadence design project.” This enhanced design flow is compatible with Tower Semiconductor’s SiGe BiCMOS and SiPho PDKs, establishing a strong foundation for the future of semiconductor design.
Cooperation and Reliability in Technology Development
With more than two decades of successful collaboration, Tower and Cadence have consistently provided mutual clients with advanced analog IC solutions, facilitating first-pass success for complex designs. Ashutosh Mauskar, VP of Product Management for Cadence, reinforced the benefits of this cooperative effort, stating that the validation of the Heterogeneous Integration flow stands to benefit customers relying on Tower technology.
Affirmation of Tower Semiconductor's Leadership
This latest expansion solidifies Tower Semiconductor’s role as a leader in 3D-IC and heterogeneous integration, fostering innovation in analog semiconductor solutions that respond to the evolving needs of next-generation markets.
Frequently Asked Questions
What is the significance of Tower Semiconductor's new technology?
This technology enhances 3D integration, supporting compact high-performance systems critical for applications such as data centers.
How does the collaboration with Cadence Design Systems benefit customers?
The partnership provides a unified design flow that facilitates efficient design processes across multiple technologies, increasing the likelihood of project success.
What applications benefit from the new CPO foundry technology?
This technology primarily benefits applications in Co-Packaged Optics, enhancing the performance and density of integrated circuits.
How long has Tower Semiconductor been in operation?
Tower Semiconductor has a long-standing history and has continually evolved, especially in high-volume production for sensor technologies.
What types of markets does Tower Semiconductor serve?
Tower Semiconductor serves several evolving markets, including consumer, automotive, medical, and industrial sectors, providing high-value analog solutions.
