The Poet platform is currently the basis for a num

The Poet platform is currently the basis for a number of key projects -- including optical code division multiple access (OCDMA) devices for avionics systems, combined RF-/optical-phased arrays, optoelectronic directional couplers and ultra-low-power random access memory (RAM).

If we just look at the memory side and review some of the background and one of the most recent appointments (announced the end of June)

Dr. Peisl has over 33 years of management experience in semiconductor research, development and marketing. He has served companies such as Siemens, Infineon, Qimonda, Ramaxel and Netlist. His people and project management background includes broad international experience in Germany, Malaysia, France, China and the United States. Dr. Peisl was directly responsible for product development of dynamic-random-access-memory (DRAM) generations from 64 megabits to one gigabyte. Additionally, he has supervised starting new product lines such as mobile random access memory, reduced-latency DRAM and DRAM-based application-specific integrated circuits. Being a decade-long member of the Joint Electron Device Engineering Council standardization committee, Dr. Peisl has chaired the development of the predecessor of the double-data-rate-two specification within the advanced DRAM technology consortium, together with technical members of Intel, Samsung, Hynix, Micron and Elpida.

Some background on this device:

Summation

ODIS has developed POET as an OE integration platform in GaAs that provides memory capability inherently in the form of a thyristor. Fundamentally, the thyristor is an inversion channel device as in the MOS transistor. The quantum well of the thyristor has steady-state and non-steady-state conditions depending upon the quantity of stored charge in the quantum wells. Original demonstrations of the thyristor memory function employed a single gating terminal to show the dynamic operation of the memory element. The thyristor enabled very high density (area determined essentially by the cross-point of an array) and negligible power consumption in the storage mode. Original conclusions were that the memory operation must be entirely electrical since emitters and detectors could not be formed with the size reduction of an ultra-small memory cell. 

However, during the Phase I effort, the disk laser and disk detector configuration were applied to a novel memory cell implementation. With this innovation, the memory size becomes the smallest possible disk that can be designed, fabricated and contacted. The density is achieved with disk separation by optical waveguide in one direction and channel contacts in the other direction. When embedded as an element in a large 2D array, optical writing and optical readout become effective methods of large memory access, 1 row at a time. The memory cell functions as an active laser for the readout function, so the limitation of minimum stored charge is eliminated. The n and p channel access contacts assist in the write, selection and erase (write 0) operations. The storage function is the ability of the thyristor to retain its memory state at very low voltage over extended times. Thus the POET optoelectronic dynamic memory cell rivals the performance of state-of-the-art DRAM or SRAM in terms of density, speed and power consumption. The predominant POET DRAM advantage is that charge is not stored in the cell and then read out by a sense amplifier (SA) resulting in a limited line length and thus density. Then the speed of readout depends on the tradeoff between the charge stored at the cell, the capacitance of the line to reach the SA and sense amp sensitivity. In contrast, the POET cell is a disk laser and the line to the SA is an optical waveguide. 

The transit time on the line is immediately improved (100µm/ps) and the capacitive effect is eliminated. The sensitivity of the thyristor SA to the optical pulse is far better than the electronic SA which means a smaller optical energy must be provided by the disk than electrical energy provided by the cell capacitor. Also there are fewer devices in the thyristor SA than the transistor SA. When coupled with the much higher speed switching in the thyristor, a larger high density memory with lower power consumption results. POET also offers the advantage that the SA can deliver data optically from the chip by waveguide or vertically. This means that memory arrays may be coupled vertically. Therefore 3D high density memory is enabled.

Anticipated Benefits

The digital processor market is several billion dollars with steady growth potential based upon an expanding PC industry. The processor market includes both digital logic and embedded memory. Another huge market for general purpose design is the Floating Point Gate Array (FPGA). Both of these markets are dominated by CMOS. However CMOS is constrained by both power and speed and is rapidly approaching the end of its scaling life. Thus a new device technology for the post CMOS era must be found. Today, silicon photonics is being pursued as a means to achieve CMOS combined with OE. However, without the laser on-chip, this approach is not a solution. Thus the opportunity for GaAs based circuits is significant. It is anticipated that GaAs will then become the dominant material base for the future IC industry because it can provide all the capabilities of CMOS together with the laser. The POET based memory cell now adds to the capability of the GaAs technology for generalized processor functions. 

The wireless industry is already using all of the GaAs amplifiers that are produced. One can therefore expect a market opportunity for GaAs based memory products with large up-side potential. Digital products can now be added to a growing number of markets addressed by integrated optoelectronics including AD converters, imager products, parallel optical data links, optical interface circuits, ocdma based systems, phased array receivers and other markets currently dominated by Si.

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