$GTCH is researching the development of a machine learning-driven, automated integrated circuits design environment, enabling Fast-Track, Design-to-Silicon capabilities. The research is focused on an unified environment that contemplates including architecture design, functional verification, full-system power analysis and comprehensive physical verification. The goal of the design environment is to improve design performance by analyzing latency area optimization, bandwidth and power. The solution that the Company is researching is aimed to support custom analog, mixed, radio frequency and synthesis designs. In addition, the Company intends that the new system will perform signoff extraction, static timing analysis (STA), robust physical verification including design for manufacturing (DFM) and electromigration.
Typically, the industry is using separate electronic design automation (EDA) tools for specific topic which creates vast integration efforts. GBT plans to offer a one-shop stop for the entire IC design flow. GBT believes that a comprehensive, highly automated flow, would enable fast-track for an IC design project by combining traditionally separate front-end and back-end chip design technologies, into one integrated flow. The automated flow is being designed to eliminate iterations between EDA tools, accelerating the design cycle and reducing the overall IC development time and costs. The system plans to support mixed signals System on a Chip (SoC), digital cores and analog IPs. The research is examining the use of the GBT’s machine learning-driven accelerators to dramatically enhance design productivity and enabling design reuse in the design environment. Deep learning algorithms will aim to provide rapid design capabilities by analyzing and optimizing circuit designs and layouts. The system will take into consideration the process design rules, reliability constraints, DFM and thermal analysis aspects. GBT believes that its research will illustrate that this type of a machine learning-driven, unified, IC design environment will provide a quantum leap in efficiency and productivity for microchip’s designers, significantly reducing the overall IC’s design time.
“We are researching an IC solution that would target small start-up companies to large corporations in the semiconductor industry with varying design requirements. With GBT’s new approach, we aim to develop a machine learning-driven, one automated IC design flow, enabling Fast-Track Design-to-Silicon for IC design houses. The way we want to do this is by combining traditionally separate front-end and back-end chip design flows into one integrated environment that accelerates the overall design cycle and reducing the IC development costs. A typical microchip design process includes many steps which are classified as front-end and back-end tasks. Various steps are executed using separate EDA tools which require vast amount of integration and design environment adjustments. The new, machine learning-driven flow that we are researching aims to provide one-stop design environment advanced capabilities, with high levels of automation, with the goal of enabling the delivery of superior quality designs, with much faster completion time. The usage of our deep learning and advanced computational geometry algorithms aims to produce a comprehensive design environment, enabling efficient digital/analog design and implementation, particularly with advanced manufacturing nodes. In addition, we are also researching incorporating other capabilities into the system which may include functional and physical verification, simulations, power optimization, characterization, or yield management. With this research we aim to standardize digital and analog IC’s design, simulation, verification and characterization. We firmly believe that a one, intelligent, automated IC
Typically, the industry is using separate electronic design automation (EDA) tools for specific topic which creates vast integration efforts. GBT plans to offer a one-shop stop for the entire IC design flow. GBT believes that a comprehensive, highly automated flow, would enable fast-track for an IC design project by combining traditionally separate front-end and back-end chip design technologies, into one integrated flow. The automated flow is being designed to eliminate iterations between EDA tools, accelerating the design cycle and reducing the overall IC development time and costs. The system plans to support mixed signals System on a Chip (SoC), digital cores and analog IPs. The research is examining the use of the GBT’s machine learning-driven accelerators to dramatically enhance design productivity and enabling design reuse in the design environment. Deep learning algorithms will aim to provide rapid design capabilities by analyzing and optimizing circuit designs and layouts. The system will take into consideration the process design rules, reliability constraints, DFM and thermal analysis aspects. GBT believes that its research will illustrate that this type of a machine learning-driven, unified, IC design environment will provide a quantum leap in efficiency and productivity for microchip’s designers, significantly reducing the overall IC’s design time.
“We are researching an IC solution that would target small start-up companies to large corporations in the semiconductor industry with varying design requirements. With GBT’s new approach, we aim to develop a machine learning-driven, one automated IC design flow, enabling Fast-Track Design-to-Silicon for IC design houses. The way we want to do this is by combining traditionally separate front-end and back-end chip design flows into one integrated environment that accelerates the overall design cycle and reducing the IC development costs. A typical microchip design process includes many steps which are classified as front-end and back-end tasks. Various steps are executed using separate EDA tools which require vast amount of integration and design environment adjustments. The new, machine learning-driven flow that we are researching aims to provide one-stop design environment advanced capabilities, with high levels of automation, with the goal of enabling the delivery of superior quality designs, with much faster completion time. The usage of our deep learning and advanced computational geometry algorithms aims to produce a comprehensive design environment, enabling efficient digital/analog design and implementation, particularly with advanced manufacturing nodes. In addition, we are also researching incorporating other capabilities into the system which may include functional and physical verification, simulations, power optimization, characterization, or yield management. With this research we aim to standardize digital and analog IC’s design, simulation, verification and characterization. We firmly believe that a one, intelligent, automated IC
