"Fundamentally, today’s advanced chips are havin

"Fundamentally, today’s advanced chips are having smaller devices with smaller geometries. The silicon areas become more compact and crowded which impacts performance, power consumption and reliability. GAA FET technology is expected to provide performance enhancement with lower power consumption, which we believe makes it attractive for design firms. Another important aspect is that GAA FET relaxes some of the problems introduced by the traditional FinFETS. The new transistor structure is designed to provide stronger device gate control which would enable better conductivity and improved electrical characteristics. This is an important factor because at the smaller nodes, we are noticing more variability, particularly for memories. But with new technologies, typically comes uncertainty. With GAA FET we can expect higher potential for variability and design rule challenges, especially with today’s billions of transistors and advanced functionalities ICs. The ever-going demand to consume minimal power and to operate with high performance using GAA FET, could become a major obstacle for design firms, delaying milestones and timelines. GBT plans to develop GAA FET support for all its EDA productivity enhancement software tools with the goal of saving significant design time, enabling IC designers to maintain competitive schedules. We are going to start with our interactive identification and correction of design rule violations program. This tool operates during the construction of an IC layout, providing an on-the-fly feedback about violations. The tool also offers automatic correction of the detected violation and could save major project’s design time. Without the appropriate level of geometrical accuracy within an affordable time frame designers might need many extra months to reach the desired signoff schedule. Design Rule identification and correction process is a critical step during signoff, and without an intelligent productivity technology an enormous amount of pressure is put on designers to achieve design closure in a timely manner.

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