$GTCH is developing Gate-All-Around FET (GAA FET) support for its integrated circuits, productivity enhancement EDA technology. The support for the Gate-All-Around FET device will be added to all GBT’s EDA tools, starting with its interactive, advice and correction of design rule violations software. This tool works on Integrated Circuit (IC) layout data, checking manufacturing geometrical and electrical design rules correctness during the construction of an IC layout, thus creating Rule-Aware mask design environment. As the microchip’s industry is accelerating towards the new 5nm and 3nm processes, vast amount of design and manufacturing efforts are invested in the next generation; 2nm node and beyond. Foundries and major chip design firms are facing numerous challenges as well as upcoming crucial uncertainties. The traditional FinFet device is planned to be replaced, starting at 3nm, by a new promising device called the ‘Gate-All-Around FET’ device. This innovative device is considered to be a superior CMOS device in terms of conductivity, scaling, and electrical characteristics. GAA FET’s performance is expected to be significantly improved, with the goal of power consumption reduction, which makes it attractive for IC design companies to stay ahead of the domain’s competition. GBT’s visual, design rule detection and correction program is operating on an IC layout database, identifying violations, and performing the necessary correction, ensuring a correct-by-construction IC design environment. This approach could save significant amount of the global project’s design time by early identification and elimination of design’s violations and flaws. GBT believes that by adding GAA FET support, design time could be reduced especially with advanced upcoming nanometer chips of 2nm and beyond. GBT plans to incorporate GAA FET support within all its EDA software tools in order to remain at the forefront of the IC design arena.
"Fundamentally, today’s advanced chips are having smaller devices with smaller geometries. The silicon areas become more compact and crowded which impacts performance, power consumption and reliability. GAA FET technology is expected to provide performance enhancement with lower power consumption, which we believe makes it attractive for design firms. Another important aspect is that GAA FET relaxes some of the problems introduced by the traditional FinFETS. The new transistor structure is designed to provide stronger device gate control which would enable better conductivity and improved electrical characteristics. This is an important factor because at the smaller nodes, we are noticing more variability, particularly for memories. But with new technologies, typically comes uncertainty. With GAA FET we can expect higher potential for variability and design rule challenges, especially with today’s billions of transistors and advanced functionalities ICs. The ever-going demand to consume minimal power and to operate with high performance using GAA FET, could become a major obstacle for design firms, delaying milestones and timelines. GBT plans to develop GAA FET support for all its EDA productivity enhancement software tools with the goal of saving significant design time, enabling IC designers to maintain competitive schedules. We are going to start with our interactive identification and correction of design rule violations program. This tool operates during the construction of an IC layout, providing an on-the-fly feedback about violations. The tool also offers automatic correction of the detected violation and could save major project’s design time. Without the appropriate level of geometrical accuracy within an affordable time frame designers might need many extra months to reach the desired signoff schedule. Design Rule identification and correction process is a critical step during signoff, and without an intelligent productivity technology an enormous amount of pressure is put on designers to achieve design closure in a timely manner. Supporting GAA FET technology will enable IC designers to achieve design closure in a timely manner, meeting or shortening desired schedules and time to market milestones” provided Danny Rittman, the Company’s CTO.
"Fundamentally, today’s advanced chips are having smaller devices with smaller geometries. The silicon areas become more compact and crowded which impacts performance, power consumption and reliability. GAA FET technology is expected to provide performance enhancement with lower power consumption, which we believe makes it attractive for design firms. Another important aspect is that GAA FET relaxes some of the problems introduced by the traditional FinFETS. The new transistor structure is designed to provide stronger device gate control which would enable better conductivity and improved electrical characteristics. This is an important factor because at the smaller nodes, we are noticing more variability, particularly for memories. But with new technologies, typically comes uncertainty. With GAA FET we can expect higher potential for variability and design rule challenges, especially with today’s billions of transistors and advanced functionalities ICs. The ever-going demand to consume minimal power and to operate with high performance using GAA FET, could become a major obstacle for design firms, delaying milestones and timelines. GBT plans to develop GAA FET support for all its EDA productivity enhancement software tools with the goal of saving significant design time, enabling IC designers to maintain competitive schedules. We are going to start with our interactive identification and correction of design rule violations program. This tool operates during the construction of an IC layout, providing an on-the-fly feedback about violations. The tool also offers automatic correction of the detected violation and could save major project’s design time. Without the appropriate level of geometrical accuracy within an affordable time frame designers might need many extra months to reach the desired signoff schedule. Design Rule identification and correction process is a critical step during signoff, and without an intelligent productivity technology an enormous amount of pressure is put on designers to achieve design closure in a timely manner. Supporting GAA FET technology will enable IC designers to achieve design closure in a timely manner, meeting or shortening desired schedules and time to market milestones” provided Danny Rittman, the Company’s CTO.
