$GTCH is developing an AI empowered technology for automatic compaction of integrated circuit (IC) layout blocks. As modern ICs are ever growing in complexity and size there is a high demand for design automation to reduce silicon area and increase its yield. Microchips are expected to include more functionalities, consuming less power, reducing in size and ultimately cheaper.
The semiconductor field is pushing the envelope by introducing smaller manufacturing processes scaling into deep nanometer ranges. Scaling down the manufacturing process enables billions of transistors on die, higher performance, and power consumption reduction, but introduces new design challenges due to complicated physics rules. IC projects may take longer time as they need to comply with a vast amount of complex design rules and constraints. It is the Company’s position that an automatic IC layout compaction technology can be an efficient way to reduce new and existing layout IPs size utilizing less silicon area with the goal of increasing the overall yield.
The main goal of the compaction process is to create the densest IC layout possible. GBT is now designing an AI empowered technology to read existing and new microchip’s layout data with the goal of producing the densest layout block possible. The technology is seeking to optimize post-layout IPs, shrinking them automatically retaining geometrical design rule and electrical connectivity correctness. In addition, a goal of the computer program is to maintain Design for Manufacturing (DFM) constraints to comply with the manufacturing process. The technology design contemplates implementing graph-based optimization algorithms and deep learning training for fast processing and optimal area utilization.
The technology is targeted for Analog, Digital, RF and MIXED integrated circuits styles with the goal of supporting GDSII and Oasis data.
With today’s ever growing microchips size and complexity there is a need for urgent Electronic Design Automation (EDA) solutions to decrease IC’s size and increase performance while decreasing cost. GBT believes that utilizing an intelligent IP block compaction technology may result in achieving these goals.
“Today’s microchips include billions of transistors which make a significant impact on the overall chip’s die size. As larger silicon ‘real-estate’ is, designers have to face more complex electrical and performance challenges. The industry is constantly scaling down the manufacturing process, reaching deep nanometer ranges which introduce more complicated physics-oriented challenges. We believe an efficient layout compaction technology can be a great functional and economical solution for existing and new IP blocks. We are now designing an AI based technology to read an existing IC layout block and compacting its size to the densest possible. The process is targeted to be done automatically and within short time. We are seeking to design the program with the goal of maintaining the process design rules, DFM guidelines and electrical connectivity correctness. It is the goal for the entire silicon area to undergo significant reduction and therefore enable improved silicon yield and ultimately cheaper ICs. The technology is planned to support older and advanced nanometer processes, Analog, Digital, RF and MIXED styles, making it a flexible tool for all types of IC design firms. As Integrated Circuits technology advances, more functionalities, lower power consumption, higher performance and lower cost are in high demand, especially within advanced nanometer projects,” stated Danny Rittman, the Company’s CTO.
The semiconductor field is pushing the envelope by introducing smaller manufacturing processes scaling into deep nanometer ranges. Scaling down the manufacturing process enables billions of transistors on die, higher performance, and power consumption reduction, but introduces new design challenges due to complicated physics rules. IC projects may take longer time as they need to comply with a vast amount of complex design rules and constraints. It is the Company’s position that an automatic IC layout compaction technology can be an efficient way to reduce new and existing layout IPs size utilizing less silicon area with the goal of increasing the overall yield.
The main goal of the compaction process is to create the densest IC layout possible. GBT is now designing an AI empowered technology to read existing and new microchip’s layout data with the goal of producing the densest layout block possible. The technology is seeking to optimize post-layout IPs, shrinking them automatically retaining geometrical design rule and electrical connectivity correctness. In addition, a goal of the computer program is to maintain Design for Manufacturing (DFM) constraints to comply with the manufacturing process. The technology design contemplates implementing graph-based optimization algorithms and deep learning training for fast processing and optimal area utilization.
The technology is targeted for Analog, Digital, RF and MIXED integrated circuits styles with the goal of supporting GDSII and Oasis data.
With today’s ever growing microchips size and complexity there is a need for urgent Electronic Design Automation (EDA) solutions to decrease IC’s size and increase performance while decreasing cost. GBT believes that utilizing an intelligent IP block compaction technology may result in achieving these goals.
“Today’s microchips include billions of transistors which make a significant impact on the overall chip’s die size. As larger silicon ‘real-estate’ is, designers have to face more complex electrical and performance challenges. The industry is constantly scaling down the manufacturing process, reaching deep nanometer ranges which introduce more complicated physics-oriented challenges. We believe an efficient layout compaction technology can be a great functional and economical solution for existing and new IP blocks. We are now designing an AI based technology to read an existing IC layout block and compacting its size to the densest possible. The process is targeted to be done automatically and within short time. We are seeking to design the program with the goal of maintaining the process design rules, DFM guidelines and electrical connectivity correctness. It is the goal for the entire silicon area to undergo significant reduction and therefore enable improved silicon yield and ultimately cheaper ICs. The technology is planned to support older and advanced nanometer processes, Analog, Digital, RF and MIXED styles, making it a flexible tool for all types of IC design firms. As Integrated Circuits technology advances, more functionalities, lower power consumption, higher performance and lower cost are in high demand, especially within advanced nanometer projects,” stated Danny Rittman, the Company’s CTO.
