$GTCH filed a continuation patent application for its 3D, multiplanar, integrated circuits (IC) design and manufacturing technology. The original invention design presents a new way to design and manufacture larger size ICs to fit advanced analog, digital and mixed type ICs on a silicon wafer. The goal of these methods is to enable advanced microchip’s design and manufacturing within less space which can be a significant factor particularly for memories, CPU, GPU, AI chips and more. The company’s 3D microchip patent was filed on March 5, 2019, and was granted as of December 1, 2020 by the United States Patent and Trademark Office (“USPTO”); U.S. Patent No. 10,854,763. The continuation application, assigned number 17102928, was filed on November 24, 2020 and seeks to broaden the protection of the main IP concepts. It is GBT’s goal to allow for further advancements in circuitries connections and wiring through the use of the 3D, multidimensional design utilizing more space on the silicon wafer. This technology aims to increase memory size capacity, speed, performance, and processing power.
“For decades, technology companies have worked to shrink microchips to fit into devices as small as a watch, an earbud or a surgical instrument. Shrinking microchips to make them smaller often means losing space on the chip for performance and functionality, so the movement has turned to three-dimensional microchips. With the hope to maintain efficiency, the ongoing problem with 3D chips is that they rely on traditional interconnectivity methods, including wire bonding and flip chips, to stack vertically. By trying to create a 3D integrated circuit, the stacking of the silicon wafers develops limitations. We believe redesigning the microchip architecture can improve production like routing and the placement of critical building blocks within the IC. One method found to help make these improvements in the architecture of the microchip includes changing the design from the stereotypical flat (or two-dimensional design) to a 3D or layered structure. We believe our approach may alleviates the disadvantages of current ICs by providing new multi-dimensional IC architecture and design. The 3D microchip patent introduces a multi-dimensional, multi-planar IC structure that may potentially be used in IC fabrication. As microchip’s are constantly getting more complex there is a need for a breakthrough technology to enable much larger silicon utilization with higher performance and lower cost. We believe that the technology contemplated by the patent continuation application can be an efficient solution, breaking new grounds in the integrated circuits field, and introducing the next generation of design and manufacturing standards,” said Danny Rittman, the Company’s CTO.
“For decades, technology companies have worked to shrink microchips to fit into devices as small as a watch, an earbud or a surgical instrument. Shrinking microchips to make them smaller often means losing space on the chip for performance and functionality, so the movement has turned to three-dimensional microchips. With the hope to maintain efficiency, the ongoing problem with 3D chips is that they rely on traditional interconnectivity methods, including wire bonding and flip chips, to stack vertically. By trying to create a 3D integrated circuit, the stacking of the silicon wafers develops limitations. We believe redesigning the microchip architecture can improve production like routing and the placement of critical building blocks within the IC. One method found to help make these improvements in the architecture of the microchip includes changing the design from the stereotypical flat (or two-dimensional design) to a 3D or layered structure. We believe our approach may alleviates the disadvantages of current ICs by providing new multi-dimensional IC architecture and design. The 3D microchip patent introduces a multi-dimensional, multi-planar IC structure that may potentially be used in IC fabrication. As microchip’s are constantly getting more complex there is a need for a breakthrough technology to enable much larger silicon utilization with higher performance and lower cost. We believe that the technology contemplated by the patent continuation application can be an efficient solution, breaking new grounds in the integrated circuits field, and introducing the next generation of design and manufacturing standards,” said Danny Rittman, the Company’s CTO.
