$GTCHD Based on the recent patent that GBT filed i

$GTCHD Based on the recent patent that GBT filed in this domain, the new tool will read the manufacturing process rule deck(s) to understand the IC design rules, guidelines and constraints. The tool will advise the user about potential design rule violations during the construction of a mask layout database, by providing a real time visual feedback. The tool is operating within a layout editor’s IC layout database recommending a necessary correction to ensure correct-by-construction IC layout. This approach could save a significant amount of the global project’s design time by early identification and elimination of design violation and flaws. The system will also include an option to automatically correct these violations, maintaining the design’s electrical connectivity, geometrical rules, and reliability rules correctness. The tool will have the capability to detect design rule violation hierarchically, and offer fix-recommendations during the construction of IC layout blocks. Over the past several years, microchip’s number of transistors has dramatically increased, prolonging a project design's time and schedule. GBT believes that by addressing potential violations early during the IC layout design phase, significant time could potentially be saved. This type of technology is estimated to save between 30%-50% of the entire physical layout design time; especially, with advanced nanometer microchips. The company intends to develop an entire family of clean-by-construction software tools in order to boost an IC project’s design time, the technology is targeted to support analog, digital and mixed signal IC’s designs.

https://www.barrons.com/articles/gbt-develops...rview_news

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