$GTCHD News: GBT Develops a Visual Design-Rule Analysis System for Integrated Circuits
Targeted to provide a robust interactive design environment for early detection and elimination of IC’s layout design rule violations.
SAN DIEGO, Nov. 23, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCHD) ("GBT” or the “Company”), is developing a nanometer range EDA tool that visually advises and eliminates design rule violations during the construction of an integrated circuit physical layout. The tool works on IC layout data and checks for design rules correctness, as specified in the process specifications (Technology file) during the construction of an IC layout, creating a Rule-Aware Mask design environment.
Based on the recent patent that GBT filed in this domain, the new tool will read the manufacturing process rule deck(s) to understand the IC design rules, guidelines and constraints. The tool will advise the user about potential design rule violations during the construction of a mask layout database, by providing a real time visual feedback. The tool is operating within a layout editor’s IC layout database recommending a necessary correction to ensure correct-by-construction IC layout. This approach could save a significant amount of the global project’s design time by early identification and elimination of design violation and flaws.
The system will also include an option to automatically correct these violations, maintaining the design’s electrical connectivity, geometrical rules, and reliability rules correctness. The tool will have the capability to detect design rule violation hierarchically, and offer fix-recommendations during the construction of IC layout blocks. Over the past several years, microchip’s number of transistors has dramatically increased, prolonging a project design's time and schedule. GBT believes that by addressing potential violations early during the IC layout design phase, significant time could potentially be saved.
This type of technology is estimated to save between 30%-50% of the entire physical layout design time; especially, with advanced nanometer microchips. The company intends to develop an entire family of clean-by-construction software tools in order to boost an IC project’s design time, the technology is targeted to support analog, digital and mixed signal IC’s designs.
"Our today’s microchip’s include billions of transistors and advanced functionalities. In addition, they need to consume minimal power and operate with high performance, it’s all a matter of optimal balance between silicon area, power constraints, speed and required functionalities. As the manufacturing process is constantly getting smaller, the semiconductor’s physics introduces new geometrical, electrical and manufacturing design rule challenges, causing significantly longer project design time, and time-to- market.
Our idea is to address potential design issues, early during the design phase. GBT’s team is currently working on a software tool to analyze and identify design rule violations during the IC layout construction phase. Similar to the 'spell-check' highlight concept, our tool will highlight potential violations as the designer is constructing and building the integrated circuit layout blocks. Although not a new concept, we will introduce a new approach that visually analyzes and alerts areas-of-interest associated with potential design violations.
This will include graphic representation and topological recommendations within the mask layout data, where a non-compliance issue was detected. Furthermore, the system will offer an automatic correction upon the user’s approval to eliminate the flaw on the spot. The tool will be based on a region analysis concept and provide multi-zones visual feedback to increase the vitality level of the reported violations.
The technology will support analog, digital and mixed IC’s design styles; including a full hierarchical support, and we predict that the technology will be mostly efficient in advanced manufacturing nodes of 7nm and below due to their acute design rule complexities. Designers will be able to design their microchips much easier, as an interactive assistance is constantly supervising them in the background, guiding them as they go, ensuring a clean-by-construction mask layout database,” said Danny Rittman, the Company’s CTO.
Targeted to provide a robust interactive design environment for early detection and elimination of IC’s layout design rule violations.
SAN DIEGO, Nov. 23, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCHD) ("GBT” or the “Company”), is developing a nanometer range EDA tool that visually advises and eliminates design rule violations during the construction of an integrated circuit physical layout. The tool works on IC layout data and checks for design rules correctness, as specified in the process specifications (Technology file) during the construction of an IC layout, creating a Rule-Aware Mask design environment.
Based on the recent patent that GBT filed in this domain, the new tool will read the manufacturing process rule deck(s) to understand the IC design rules, guidelines and constraints. The tool will advise the user about potential design rule violations during the construction of a mask layout database, by providing a real time visual feedback. The tool is operating within a layout editor’s IC layout database recommending a necessary correction to ensure correct-by-construction IC layout. This approach could save a significant amount of the global project’s design time by early identification and elimination of design violation and flaws.
The system will also include an option to automatically correct these violations, maintaining the design’s electrical connectivity, geometrical rules, and reliability rules correctness. The tool will have the capability to detect design rule violation hierarchically, and offer fix-recommendations during the construction of IC layout blocks. Over the past several years, microchip’s number of transistors has dramatically increased, prolonging a project design's time and schedule. GBT believes that by addressing potential violations early during the IC layout design phase, significant time could potentially be saved.
This type of technology is estimated to save between 30%-50% of the entire physical layout design time; especially, with advanced nanometer microchips. The company intends to develop an entire family of clean-by-construction software tools in order to boost an IC project’s design time, the technology is targeted to support analog, digital and mixed signal IC’s designs.
"Our today’s microchip’s include billions of transistors and advanced functionalities. In addition, they need to consume minimal power and operate with high performance, it’s all a matter of optimal balance between silicon area, power constraints, speed and required functionalities. As the manufacturing process is constantly getting smaller, the semiconductor’s physics introduces new geometrical, electrical and manufacturing design rule challenges, causing significantly longer project design time, and time-to- market.
Our idea is to address potential design issues, early during the design phase. GBT’s team is currently working on a software tool to analyze and identify design rule violations during the IC layout construction phase. Similar to the 'spell-check' highlight concept, our tool will highlight potential violations as the designer is constructing and building the integrated circuit layout blocks. Although not a new concept, we will introduce a new approach that visually analyzes and alerts areas-of-interest associated with potential design violations.
This will include graphic representation and topological recommendations within the mask layout data, where a non-compliance issue was detected. Furthermore, the system will offer an automatic correction upon the user’s approval to eliminate the flaw on the spot. The tool will be based on a region analysis concept and provide multi-zones visual feedback to increase the vitality level of the reported violations.
The technology will support analog, digital and mixed IC’s design styles; including a full hierarchical support, and we predict that the technology will be mostly efficient in advanced manufacturing nodes of 7nm and below due to their acute design rule complexities. Designers will be able to design their microchips much easier, as an interactive assistance is constantly supervising them in the background, guiding them as they go, ensuring a clean-by-construction mask layout database,” said Danny Rittman, the Company’s CTO.
