$GTCH News Out: SAN DIEGO, Oct. 05, 2021 (GLOBE NE
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Posted On: 10/06/2021 7:29:30 AM
$GTCH News Out: SAN DIEGO, Oct. 05, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), is researching to automate integrated circuits electrical connectivity mismatches correction to achieve faster and more efficient designs; particularly, for advanced nanometer range of 5nm and below. The project’s internal code name is SIGMA. A provisional application was filed on September 27, 2021 in the U.S. Patent and Trademark Office (“USPTO”). The application has been assigned serial number 63248550 with the USPTO.
In the past decade the IC industry has experienced exponential improvements in design and manufacturing domains. As science continues to overcome physics and electrical obstacles, these barriers are constantly moving. An IC design flow comprises of stages which involve software tools that architect, capture, simulate and verify the IC’s correctness. These computer-aided-design (CAD), also called EDA (Electronic Design Automation) are key aspects in transforming product’s definition and circuit concepts into production-ready IC design. One of the must have tools is the Layout-Vs-Schematics computer program (also called LVS verification), which verifies the electrical connectivity of an IC layout against its schematic diagram. Mismatches mean a non-functional chip or wrong electrical functionalities. Typically, in custom and semi-custom IC layout styles, these corrections must be done manually which is a significant time-consuming process. GBT is researching to develop an LVS Auto-Correct computer program for IC layout electrical connectivity mismatch corrections. The system will read an IC’s schematic and layout data, compare their electrical connectivity and in case of mismatches detection, disconnect, and re-route creating a correct electrical connection. The system will take into consideration the process design rules, reliability constraints and DFM (Design for Manufacturing) aspects. GBT believes that such an automation tool will majorly reduce the overall IC’s design time and time to market.
“A typical microchip design process includes many steps. After the IC’s specification and architecture stage, a schematic diagram that represents the integrated circuit is prepared. The schematic diagram provides a representation of the logical connections between the logic elements that form the integrated circuit. Once the schematic diagram has been tested to verify that the circuit performs the correct functions, the schematic diagram is converted into a mask layout database that includes a series of polygons. These polygons may represent the logic elements and the logical connections from the schematic diagram. The mask layout database is then used to form a series of photomasks, also known as masks or reticles, that may be used to manufacture the different layers of the integrated circuit. Typically, the mask layout database is created manually by a mask designer or automatically by a synthesis tool. Once the mask layout database is complete; polygons that form electrical connections in the mask layout database are compared to the logical connections from the schematic diagram. This comparison, called LVS (Layout-vs-Schematic) may result in connection mismatches between the schematic diagram and the mask layout database. A connection mismatch typically, indicates that an electrical connection in the mask layout database does not match its corresponding logical connection in the schematic diagram, which may cause a circuit malfunction or wrong operation. A correction of electrical connectivity mismatches within an IC data can be a significant time-consuming process; especially, with advanced nanometer chips like 5nm and below. These are exponentially growing, and include billions of transistors, which is why we are researching to develop an automated LVS correction system. Such a system will analyze an entire chips data, check for electrical connectivity mismatches, and Auto-Correct them with a click of a button. The correction process will be involved with identifying existing mismatch connections, disconnect them, and re-route correctly. The process is targeted to take minutes, which as typically, takes days to fix manually. We plan to incorporate our neural networks and advanced computational geometry algorithms to achieve these functionalities. We have already filed a provisional patent to protect the project’s system and methods and will file a non-provisional patent in the upcoming months to protect the IP. We firmly believe that such a system can become a significant productivity enhancement tool for all IC design firms; one to significantly, reduce their project’s design times and bringing them faster to the market.” Stated Danny Rittman, the Company’s CTO.
In the past decade the IC industry has experienced exponential improvements in design and manufacturing domains. As science continues to overcome physics and electrical obstacles, these barriers are constantly moving. An IC design flow comprises of stages which involve software tools that architect, capture, simulate and verify the IC’s correctness. These computer-aided-design (CAD), also called EDA (Electronic Design Automation) are key aspects in transforming product’s definition and circuit concepts into production-ready IC design. One of the must have tools is the Layout-Vs-Schematics computer program (also called LVS verification), which verifies the electrical connectivity of an IC layout against its schematic diagram. Mismatches mean a non-functional chip or wrong electrical functionalities. Typically, in custom and semi-custom IC layout styles, these corrections must be done manually which is a significant time-consuming process. GBT is researching to develop an LVS Auto-Correct computer program for IC layout electrical connectivity mismatch corrections. The system will read an IC’s schematic and layout data, compare their electrical connectivity and in case of mismatches detection, disconnect, and re-route creating a correct electrical connection. The system will take into consideration the process design rules, reliability constraints and DFM (Design for Manufacturing) aspects. GBT believes that such an automation tool will majorly reduce the overall IC’s design time and time to market.
“A typical microchip design process includes many steps. After the IC’s specification and architecture stage, a schematic diagram that represents the integrated circuit is prepared. The schematic diagram provides a representation of the logical connections between the logic elements that form the integrated circuit. Once the schematic diagram has been tested to verify that the circuit performs the correct functions, the schematic diagram is converted into a mask layout database that includes a series of polygons. These polygons may represent the logic elements and the logical connections from the schematic diagram. The mask layout database is then used to form a series of photomasks, also known as masks or reticles, that may be used to manufacture the different layers of the integrated circuit. Typically, the mask layout database is created manually by a mask designer or automatically by a synthesis tool. Once the mask layout database is complete; polygons that form electrical connections in the mask layout database are compared to the logical connections from the schematic diagram. This comparison, called LVS (Layout-vs-Schematic) may result in connection mismatches between the schematic diagram and the mask layout database. A connection mismatch typically, indicates that an electrical connection in the mask layout database does not match its corresponding logical connection in the schematic diagram, which may cause a circuit malfunction or wrong operation. A correction of electrical connectivity mismatches within an IC data can be a significant time-consuming process; especially, with advanced nanometer chips like 5nm and below. These are exponentially growing, and include billions of transistors, which is why we are researching to develop an automated LVS correction system. Such a system will analyze an entire chips data, check for electrical connectivity mismatches, and Auto-Correct them with a click of a button. The correction process will be involved with identifying existing mismatch connections, disconnect them, and re-route correctly. The process is targeted to take minutes, which as typically, takes days to fix manually. We plan to incorporate our neural networks and advanced computational geometry algorithms to achieve these functionalities. We have already filed a provisional patent to protect the project’s system and methods and will file a non-provisional patent in the upcoming months to protect the IP. We firmly believe that such a system can become a significant productivity enhancement tool for all IC design firms; one to significantly, reduce their project’s design times and bringing them faster to the market.” Stated Danny Rittman, the Company’s CTO.
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