$GTCH “A typical microchip design process includes many steps. After the IC’s specification and architecture stage, a schematic diagram that represents the integrated circuit is prepared. The schematic diagram provides a representation of the logical connections between the logic elements that form the integrated circuit. Once the schematic diagram has been tested to verify that the circuit performs the correct functions, the schematic diagram is converted into a mask layout database that includes a series of polygons. These polygons may represent the logic elements and the logical connections from the schematic diagram. The mask layout database is then used to form a series of photomasks, also known as masks or reticles, that may be used to manufacture the different layers of the integrated circuit. Typically, the mask layout database is created manually by a mask designer or automatically by a synthesis tool. Once the mask layout database is complete; polygons that form electrical connections in the mask layout database are compared to the logical connections from the schematic diagram. This comparison, called LVS (Layout-vs-Schematic) may result in connection mismatches between the schematic diagram and the mask layout database. A connection mismatch typically, indicates that an electrical connection in the mask layout database does not match its corresponding logical connection in the schematic diagram, which may cause a circuit malfunction or wrong operation. A correction of electrical connectivity mismatches within an IC data can be a significant time-consuming process; especially, with advanced nanometer chips like 5nm and below. These are exponentially growing, and include billions of transistors, which is why we are researching to develop an automated LVS correction system. Such a system will analyze an entire chips data, check for electrical connectivity mismatches, and Auto-Correct them with a click of a button. The correction process will be involved with identifying existing mismatch connections, disconnect them, and re-route correctly. The process is targeted to take minutes, which as typically, takes days to fix manually. We plan to incorporate our neural networks and advanced computational geometry algorithms to achieve these functionalities. We have already filed a provisional patent to protect the project’s system and methods and will file a non-provisional patent in the upcoming months to protect the IP. We firmly believe that such a system can become a significant productivity enhancement tool for all IC design firms; one to significantly, reduce their project’s design times and bringing them faster to the market.” Stated Danny Rittman, the Company’s CTO.
https://seekingalpha.com/pr/18499372-gbt-is-r...faster-and
https://seekingalpha.com/pr/18499372-gbt-is-r...faster-and
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