$GTCH now developing EDA (Electronic Design Automa

$GTCH now developing EDA (Electronic Design Automation) software technology to automate the generation of reusable ICs layout blocks Intellectual property (IPs). Semiconductor Intellectual Property (IP) is a reusable logic or layout unit design. An automatic IP layout generator can enable significant time reduction by designing complete IP blocks that can be reused in wide verity of IC projects. Many of today’s IC’s functionalities are integrated into single chips that are called System on Chip (SoC). A SoC is an integrated circuit that integrates electronic and computer components on it. It is consistent of core blocks each performing its own task, for example internal memory, storage, central processing unit (CPU), input/output ports (USB, HDMI), graphic processing units, analog circuitries, radio and more. In modern SoC’s there are also AI and other complex blocks to enable advanced capabilities. Using reusable, pre-designed IP cores/blocks is becoming more and more crucial to minimize the entire IC design time.

GBT is now designing a new EDA software tool to automatically generate integrated circuits layout IP blocks. The tool will read process design rules, constraints, and detailed system specifications and automatically generate an IP layout block. The primary technology’s goal is to reduce an IC project’s design and costs, as well as, the silicon space occupied by large systems. An efficient SoC design consumes low power, offering high performance, within a smaller physical space. Using automatic IP block generator will enable faster and cheaper SoC’s design, making it possible to create a world of intelligent electronic devices in wide variety of domains.