$GTCH (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), is developing EDA (Electronic Design Automation) software technology to automate the generation of reusable ICs layout blocks Intellectual property (IPs). Semiconductor Intellectual Property (IP) is a reusable logic or layout unit design. An automatic IP layout generator can enable significant time reduction by designing complete IP blocks that can be reused in wide verity of IC projects.
Many of today’s IC’s functionalities are integrated into single chips that are called System on Chip (SoC). A SoC is an integrated circuit that integrates electronic and computer components on it. It is consistent of core blocks each performing its own task, for example internal memory, storage, central processing unit (CPU), input/output ports (USB, HDMI), graphic processing units, analog circuitries, radio and more.
In modern SoC’s there are also AI and other complex blocks to enable advanced capabilities. Using reusable, pre-designed IP cores/blocks is becoming more and more crucial to minimize the entire IC design time.
GBT is now designing a new EDA software tool to automatically generate integrated circuits layout IP blocks. The tool will read process design rules, constraints, and detailed system specifications and automatically generate an IP layout block. The primary technology’s goal is to reduce an IC project’s design and costs, as well as, the silicon space occupied by large systems. An efficient SoC design consumes low power, offering high performance, within a smaller physical space. Using automatic IP block generator will enable faster and cheaper SoC’s design, making it possible to create a world of intelligent electronic devices in wide variety of domains.
“Why reinventing the wheel with every IC design project? Especially with re-using existing features. That’s exactly what we aim to create with this new technology. An SoC chip is well described by its name. It’s an integrated circuit system that includes sub-systems on it. Each sub-system is consistent of a core block and these blocks are connected to create an entire functional system. Many of these blocks can be reusable for future projects for example, USB port, HDMI, graphic processing, wireless unit and more. Instead of re-design them every time from scratch, a pre-designed IP block can be used to save time.
Simply by using plug-and-play method. We are now designing an EDA software tool for automatic generation of IP layout blocks that can be reused unlimited times across SOC designs. For example, a microprocessor chip includes a wide variety of sub-systems for functionalities that can be standardized as IP blocks. The technology is manufacturing process aware to support older and advanced nanometer processes, making it a flexible tool for IC design firms.
As Integrated Circuits technology advances, more functionalities, lower power consumption, higher performance and lower cost are in high demand, especially with advanced nanometer projects. An automatic IP layout block generator will offer the capability to create the necessary sub-systems at a very short time, enabling much faster and cheaper IC projects designs. Ultimately it will majorly reduce project’s time-to-market, design efforts and cost, creating a whole world of IC designs possibilities,” stated Danny Rittman, the Company’s CTO.
Many of today’s IC’s functionalities are integrated into single chips that are called System on Chip (SoC). A SoC is an integrated circuit that integrates electronic and computer components on it. It is consistent of core blocks each performing its own task, for example internal memory, storage, central processing unit (CPU), input/output ports (USB, HDMI), graphic processing units, analog circuitries, radio and more.
In modern SoC’s there are also AI and other complex blocks to enable advanced capabilities. Using reusable, pre-designed IP cores/blocks is becoming more and more crucial to minimize the entire IC design time.
GBT is now designing a new EDA software tool to automatically generate integrated circuits layout IP blocks. The tool will read process design rules, constraints, and detailed system specifications and automatically generate an IP layout block. The primary technology’s goal is to reduce an IC project’s design and costs, as well as, the silicon space occupied by large systems. An efficient SoC design consumes low power, offering high performance, within a smaller physical space. Using automatic IP block generator will enable faster and cheaper SoC’s design, making it possible to create a world of intelligent electronic devices in wide variety of domains.
“Why reinventing the wheel with every IC design project? Especially with re-using existing features. That’s exactly what we aim to create with this new technology. An SoC chip is well described by its name. It’s an integrated circuit system that includes sub-systems on it. Each sub-system is consistent of a core block and these blocks are connected to create an entire functional system. Many of these blocks can be reusable for future projects for example, USB port, HDMI, graphic processing, wireless unit and more. Instead of re-design them every time from scratch, a pre-designed IP block can be used to save time.
Simply by using plug-and-play method. We are now designing an EDA software tool for automatic generation of IP layout blocks that can be reused unlimited times across SOC designs. For example, a microprocessor chip includes a wide variety of sub-systems for functionalities that can be standardized as IP blocks. The technology is manufacturing process aware to support older and advanced nanometer processes, making it a flexible tool for IC design firms.
As Integrated Circuits technology advances, more functionalities, lower power consumption, higher performance and lower cost are in high demand, especially with advanced nanometer projects. An automatic IP layout block generator will offer the capability to create the necessary sub-systems at a very short time, enabling much faster and cheaper IC projects designs. Ultimately it will majorly reduce project’s time-to-market, design efforts and cost, creating a whole world of IC designs possibilities,” stated Danny Rittman, the Company’s CTO.
