$GTCH These system and methods automatically corre

$GTCH These system and methods automatically correct the IC layout without any manual intervention, maintaining its electrical connectivity while keeping compliance with Design For Manufacturing (DFM) and Reliability Verification (RV) constraints. A typical process of manual correction of design rule violations may take several hours or even days, per layout block; and significantly, increases the overall design time. The invention protects a system that can do the correction within minutes using Artificial Intelligence and neural networks algorithms. Another important aspect is the capability of the system to perform a full hierarchical correction throughout the microchip’s sub-blocks. The number and complexity of a microchip’s design rules have been dramatically increased over the recent decade especially in advanced nanometer process of 7nm and below. This creates a bottleneck of designing advanced chips in a reasonable time due to the design rule violation complexity and amount. With a click-of-a-button this invention automatically fixes design rule violations with and can be a major IC layout productivity enhancement system, enabling higher silicon yield, brining microchip’s to market more quickly. IC design firms will benefit designing smaller chips, faster and much cheaper, which will create many new markets and opportunities.

https://www.nasdaq.com/press-release/gbt-file...-automatic

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