$GTCH (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT” or the “Company”), filed a nonprovisional patent application for ICs automatic design rule correction system and method; application #17391292 with the U.S. Patent and Trademark Office (“USPTO”). The patent protects systems and methods for automatic correction of geometrical design rule violations which typically takes vast amount of time to correct manually.
These system and methods automatically correct the IC layout without any manual intervention, maintaining its electrical connectivity while keeping compliance with Design For Manufacturing (DFM) and Reliability Verification (RV) constraints. A typical process of manual correction of design rule violations may take several hours or even days, per layout block; and significantly, increases the overall design time. The invention protects a system that can do the correction within minutes using Artificial Intelligence and neural networks algorithms. Another important aspect is the capability of the system to perform a full hierarchical correction throughout the microchip’s sub-blocks. The number and complexity of a microchip’s design rules have been dramatically increased over the recent decade especially in advanced nanometer process of 7nm and below. This creates a bottleneck of designing advanced chips in a reasonable time due to the design rule violation complexity and amount. With a click-of-a-button this invention automatically fixes design rule violations with and can be a major IC layout productivity enhancement system, enabling higher silicon yield, brining microchip’s to market more quickly. IC design firms will benefit designing smaller chips, faster and much cheaper, which will create many new markets and opportunities.
"This patent is a major game changer especially for advanced microchips of 7nm and below. As microchip’s manufacturing processes design rules are constantly getting more complex. There is a need for enhancement technology to shorten the vast amount of time invested in manual correction. Design rules are constraints dictated by the fabrication process and must be obeyed to correctly manufacture the integrated circuit. This invention protects a system and method for automatic correction of geometrical design rules while maintaining the electrical connectivity and other essential rules like reliability and DFM constraints. This type of system is a significant productivity enhancer tool within any IC’s design flow and will majorly reduce the overall chip’s design time including, time to market factor. Additionally, design changes and modifications will be able to be performed much faster and more efficiently. Microchips will be able to be made faster, smaller and with increased silicon yield, enabling a much higher profit margin. We strongly believe that this technology will create a new standard in this arena enabling the production of more integrated circuits in a much shorter time and with lower costs.”
These system and methods automatically correct the IC layout without any manual intervention, maintaining its electrical connectivity while keeping compliance with Design For Manufacturing (DFM) and Reliability Verification (RV) constraints. A typical process of manual correction of design rule violations may take several hours or even days, per layout block; and significantly, increases the overall design time. The invention protects a system that can do the correction within minutes using Artificial Intelligence and neural networks algorithms. Another important aspect is the capability of the system to perform a full hierarchical correction throughout the microchip’s sub-blocks. The number and complexity of a microchip’s design rules have been dramatically increased over the recent decade especially in advanced nanometer process of 7nm and below. This creates a bottleneck of designing advanced chips in a reasonable time due to the design rule violation complexity and amount. With a click-of-a-button this invention automatically fixes design rule violations with and can be a major IC layout productivity enhancement system, enabling higher silicon yield, brining microchip’s to market more quickly. IC design firms will benefit designing smaller chips, faster and much cheaper, which will create many new markets and opportunities.
"This patent is a major game changer especially for advanced microchips of 7nm and below. As microchip’s manufacturing processes design rules are constantly getting more complex. There is a need for enhancement technology to shorten the vast amount of time invested in manual correction. Design rules are constraints dictated by the fabrication process and must be obeyed to correctly manufacture the integrated circuit. This invention protects a system and method for automatic correction of geometrical design rules while maintaining the electrical connectivity and other essential rules like reliability and DFM constraints. This type of system is a significant productivity enhancer tool within any IC’s design flow and will majorly reduce the overall chip’s design time including, time to market factor. Additionally, design changes and modifications will be able to be performed much faster and more efficiently. Microchips will be able to be made faster, smaller and with increased silicon yield, enabling a much higher profit margin. We strongly believe that this technology will create a new standard in this arena enabling the production of more integrated circuits in a much shorter time and with lower costs.”
