$GTCH the application number 63197635 with the U.S. Patent and Trademark Office (“USPTO”). The patent protects IP for automatic correction of manufacturing process geometrical design rules violations in microchips layout data (Professional term; DRC).
Typically, a mask layout database is created manually by a layout designer or automatically by a synthesis tool. Once the mask layout database is complete, it must go through a series of verifications in few domains. One of these checks is geometrical, to check featured dimensions according to the manufacturing process rules. Today, most of the design rule violations in the mask layout database are corrected manually by a layout designer, mainly with Analog and MIXED layout types. The designer finds each violation and manually corrects the violations by moving/modifying polygons associated with the violations. During the correction process, the layout designer may create new design rule violations and therefore the correction process may be repeated until the mask layout database does not include any design rule violations. The process of iteratively correcting the design rule violations may take several hours or even days to complete and typically significantly increase the overall layout design time. The additional time required to complete layout may also delay the production of a photomask set used to fabricate the integrated circuit.
The invention includes a method and system for automatic correction of an IC layout design rule violations to match the process rule deck reference. The automatic correction, once implemented maintains the integrated circuit mask layout electrical connectivity (LVS), reliability (RV) and Design for Manufacturing (DFM) correctness. The number of design rules has been dramatically increased over the years especially in advanced nanometer process of 7nm and below. In addition, geometrical design rules became more convoluted and highly complex to comply which requires vast amount of manual correction. Using the invention once fully developed, GBT predicts a significant IC layout productivity enhancement, enabling higher silicon yield and faster microchip’s time to market. Fabless IC design firms will be able to design and manufacture their chips faster and with lower cost.
“This type of system is a significant productivity enhancer tool within IC’s design flow and will majorly reduce the global layout design time and chip’s overall time to market factor. In addition, microchips will be able to be made smaller, which increase the silicon yield enabling much higher profit margin. Project’s design time will shrink and fabless IC design firms will be able to design more advanced chips in less time. We strongly believe that this technology will make a major impact in this arena and now working on a nonprovisional application as also on future development of such commercial EDA tool”… Said Dany Rittman, the Company’s CTO.
Typically, a mask layout database is created manually by a layout designer or automatically by a synthesis tool. Once the mask layout database is complete, it must go through a series of verifications in few domains. One of these checks is geometrical, to check featured dimensions according to the manufacturing process rules. Today, most of the design rule violations in the mask layout database are corrected manually by a layout designer, mainly with Analog and MIXED layout types. The designer finds each violation and manually corrects the violations by moving/modifying polygons associated with the violations. During the correction process, the layout designer may create new design rule violations and therefore the correction process may be repeated until the mask layout database does not include any design rule violations. The process of iteratively correcting the design rule violations may take several hours or even days to complete and typically significantly increase the overall layout design time. The additional time required to complete layout may also delay the production of a photomask set used to fabricate the integrated circuit.
The invention includes a method and system for automatic correction of an IC layout design rule violations to match the process rule deck reference. The automatic correction, once implemented maintains the integrated circuit mask layout electrical connectivity (LVS), reliability (RV) and Design for Manufacturing (DFM) correctness. The number of design rules has been dramatically increased over the years especially in advanced nanometer process of 7nm and below. In addition, geometrical design rules became more convoluted and highly complex to comply which requires vast amount of manual correction. Using the invention once fully developed, GBT predicts a significant IC layout productivity enhancement, enabling higher silicon yield and faster microchip’s time to market. Fabless IC design firms will be able to design and manufacture their chips faster and with lower cost.
“This type of system is a significant productivity enhancer tool within IC’s design flow and will majorly reduce the global layout design time and chip’s overall time to market factor. In addition, microchips will be able to be made smaller, which increase the silicon yield enabling much higher profit margin. Project’s design time will shrink and fabless IC design firms will be able to design more advanced chips in less time. We strongly believe that this technology will make a major impact in this arena and now working on a nonprovisional application as also on future development of such commercial EDA tool”… Said Dany Rittman, the Company’s CTO.
