$GTCH filed with the UNITED STATES PATENT AND TRAD
Post# of 8462
The patent seeks to protect systems and methods to check and correct microchips layout for reliability violations. The underlying technology contemplates allowing IC designers to be able to analyze and fix circuits more efficiently, in real-time, and get visibility into electrical issues early during the design stages. GBT intends to target microchip’s early design stages electrical and power analysis in order to identify potential failures and provide an on-the-fly solution with the intended goal of saving weeks to months of engineering design time. The technology underlying the patent is targeted to enhance design team productivity and microchip performance for custom and synthesized ICs by enabling testing and improving/correcting of reliability issues to avoid failures. The technology includes real time electrical analysis capability. The technology is empowered by the company’s AI capabilities for rapid image recognition and vast data analysis, especially for advanced manufacturing nodes like 5nm and below. The patent application is targeted for old and new manufacturing technologies, including 7nm, 5nm and below.