$GTCH "Advanced integrated circuits mask layout design is becoming more challenging particularly due to the fact that geometries are getting smaller and more complex. Microchip’s reliability models are based on physics-of-failure mechanisms and as manufacturing processes goes smaller electrical issues significantly rise. The industry continuously scaling down semiconductor feature sizes which raises challenges in developing reliable electronic circuits with the constant demand for lower power consumption and more features. We have developed a system and method with the intended goal to analyze IC mask layout data for reliability issues, identifying “weak-spots” that are prone for failure. Giving a simplistic example, if an electrical current is supposed to flow in a chip’s metal wire that is too thin, it will melt the wire like a fuse effect. The filed patent describes a real time method to analyze this wire early during the chip’s design stage, and alerting the designer to make it wider. In this way the chip’s electronic circuits are pre-analyzed by construction, maintaining the chip’s reliability and efficient power consumption and distribution which in theory will allow Integrated circuits to function longer, consume less power and overheat less. This invention describes an on-the-fly electrical analysis to enable chip designers to address these reliability issues early during the design stage, keeping their hands on the pulse of the entire project's power management and overall performance.” Said Danny Rittman the Company’s CTO.
https://www.marketwatch.com/press-release/gbt...ws_seemore
https://www.marketwatch.com/press-release/gbt...ws_seemore
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