$GTCH “The quest to comply with DFM rules has become a true challenge, especially as we dive into advanced nanometer nodes. As part of our ongoing EDA R&D efforts we identified IC verification domains that are a bottleneck for design schedules and time to market factors. We already addressed major time-consuming topics in this area which are geometrical rules (DRC) and reliability verification (RV). As we expand our EDA physical design solutions, we plan to address DFM (Design for Manufacturing) recommended rules, combining them with DRC rules to enable robust analytics to shortened advanced nodes ICs design while obeying power constraints and performance to increase the silicon yield. Ultimately all physical aspects of a microchip design affect each other and have mutual implications. Therefore, our approach is to address them together within one integrated analysis, including their dependencies. We believe that this is the best way to deliver a comprehensive, effective DFM aware solution. By taking into effect the IC’s design area, the DRC and the DFM recommended rules we aim to significantly improve the yield, especially for deep nanometer nodes like 5nm and below. With this approach, we target to implement machine learning IC physical layout statistical modeling for critical areas analysis and other manufacturing related topics. We truly believe that only by addressing these topics as one homogenous EDA solution, an effective signoff design for DFM can be achieved” stated Danny Rittman, the Company’s CTO.
https://www.benzinga.com/pressreleases/21/03/...ufacturing
https://www.benzinga.com/pressreleases/21/03/...ufacturing
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