$GTCH GBT Technologies Inc. (OTC PINK: GTCH) ("GBT” or the “Company”), is seeking to develop a new EDA (Electronic Design Automation) technology to achieve IC’s better DFM (Design For Manufacturing) analysis.
As Integrated Circuits (IC) technology advances, manufacturing and complexity are constantly growing. Microchips are being scaled down to meet the never-ending increasing demand for more functionalities, lower power consumption, higher performance and lower cost, creating major design and manufacturing challenges. Especially with deep nanometer chips, manufacturing is facing massive challenges in terms of silicon manufacturability, and yield efficiency. Power-Performance-Area (PPA), performance and design power constraints are making turnaround schedules for manufacturers difficult to achieve. GBT commenced a research and development efforts to introduce an analytical system and method to address yield considerations to help produce IC designs with the goal of providing more yield efficient. The EDA R&D efforts will be concentrating on DFM rules analysis, physical layout geometrical rules (DRC) and nanometer silicon modeling. The planned solution will be a real-time, interactive guiding system with the goal of enabling DFM advice/auto-correction early during the microchip’s design stage. GBT already started to address a key dependency between manufacturing and IC design; the Design Rule Check (DRC) aspect. IC DRC rules are geometrical design constraints, imposed by the manufacturing process. These constraints are enforced due to manufacturing process limitations and typically required long design time to achieve compliance. The new approach will target to embed DFM manufacturing rules along with geometrical rules check (DRC) to advise designers with the goal of making their IC design more compatible for manufacturing. The goal is to increase silicon yield, obeying to power and performance constraints, through early adherence of DFM rules, rather than complying only with DRC rules.
“The quest to comply with DFM rules has become a true challenge, especially as we dive into advanced nanometer nodes. As part of our ongoing EDA R&D efforts we identified IC verification domains that are a bottleneck for design schedules and time to market factors. We already addressed major time-consuming topics in this area which are geometrical rules (DRC) and reliability verification (RV). As we expand our EDA physical design solutions, we plan to address DFM (Design for Manufacturing) recommended rules, combining them with DRC rules to enable robust analytics to shortened advanced nodes ICs design while obeying power constraints and performance to increase the silicon yield. Ultimately all physical aspects of a microchip design affect each other and have mutual implications. Therefore, our approach is to address them together within one integrated analysis, including their dependencies. We believe that this is the best way to deliver a comprehensive, effective DFM aware solution. By taking into effect the IC’s design area, the DRC and the DFM recommended rules we aim to significantly improve the yield, especially for deep nanometer nodes like 5nm and below. With this approach, we target to implement machine learning IC physical layout statistical modeling for critical areas analysis and other manufacturing related topics. We truly believe that only by addressing these topics as one homogenous EDA solution, an effective signoff design for DFM can be achieved” stated Danny Rittman, the Company’s CTO.
As Integrated Circuits (IC) technology advances, manufacturing and complexity are constantly growing. Microchips are being scaled down to meet the never-ending increasing demand for more functionalities, lower power consumption, higher performance and lower cost, creating major design and manufacturing challenges. Especially with deep nanometer chips, manufacturing is facing massive challenges in terms of silicon manufacturability, and yield efficiency. Power-Performance-Area (PPA), performance and design power constraints are making turnaround schedules for manufacturers difficult to achieve. GBT commenced a research and development efforts to introduce an analytical system and method to address yield considerations to help produce IC designs with the goal of providing more yield efficient. The EDA R&D efforts will be concentrating on DFM rules analysis, physical layout geometrical rules (DRC) and nanometer silicon modeling. The planned solution will be a real-time, interactive guiding system with the goal of enabling DFM advice/auto-correction early during the microchip’s design stage. GBT already started to address a key dependency between manufacturing and IC design; the Design Rule Check (DRC) aspect. IC DRC rules are geometrical design constraints, imposed by the manufacturing process. These constraints are enforced due to manufacturing process limitations and typically required long design time to achieve compliance. The new approach will target to embed DFM manufacturing rules along with geometrical rules check (DRC) to advise designers with the goal of making their IC design more compatible for manufacturing. The goal is to increase silicon yield, obeying to power and performance constraints, through early adherence of DFM rules, rather than complying only with DRC rules.
“The quest to comply with DFM rules has become a true challenge, especially as we dive into advanced nanometer nodes. As part of our ongoing EDA R&D efforts we identified IC verification domains that are a bottleneck for design schedules and time to market factors. We already addressed major time-consuming topics in this area which are geometrical rules (DRC) and reliability verification (RV). As we expand our EDA physical design solutions, we plan to address DFM (Design for Manufacturing) recommended rules, combining them with DRC rules to enable robust analytics to shortened advanced nodes ICs design while obeying power constraints and performance to increase the silicon yield. Ultimately all physical aspects of a microchip design affect each other and have mutual implications. Therefore, our approach is to address them together within one integrated analysis, including their dependencies. We believe that this is the best way to deliver a comprehensive, effective DFM aware solution. By taking into effect the IC’s design area, the DRC and the DFM recommended rules we aim to significantly improve the yield, especially for deep nanometer nodes like 5nm and below. With this approach, we target to implement machine learning IC physical layout statistical modeling for critical areas analysis and other manufacturing related topics. We truly believe that only by addressing these topics as one homogenous EDA solution, an effective signoff design for DFM can be achieved” stated Danny Rittman, the Company’s CTO.
