$GTCH's 3D microchip patent received a grant date
Post# of 17844
(Total Views: 114)
Posted On: 11/27/2020 8:01:32 AM
$GTCH's 3D microchip patent received a grant date as of December 1, 2020 by the United States Patent and Trademark Office (“USPTO”); U.S. Patent No. 10,854,763. The Company filed for this patent on March 5, 2019.
The invention relates to the field of integrated circuit (IC) silicon structure, and more particularly to multi-dimensional, multi-planar microchips. This patent covers GBT's futuristic integrated circuit technology which introduces new methods for microchip's manufacturing. The concept presents a new die structure and orientation. The Company believes that the new methods are efficient for all manufacturing nodes and especially for deep nanometer ranges. The technology enables the manufacturing of more transistors on a silicon wafer in order to place more circuits/features on a die. The new manufacturing architecture enables larger designs within smaller areas and significantly increases the silicon yield. The invention supports analog, RF, digital, MIXED and MEMS designs. We believe that it has the potential to revolutionize integrated circuits manufacturing and packaging, enabling huge chips on affordable silicon areas. It may be especially significant when it comes to heavily area-dependent ICs, for example memory chips, MEMS (Micro-Electro-Mechanical Systems) and micro solar cells.
The invention relates to the field of integrated circuit (IC) silicon structure, and more particularly to multi-dimensional, multi-planar microchips. This patent covers GBT's futuristic integrated circuit technology which introduces new methods for microchip's manufacturing. The concept presents a new die structure and orientation. The Company believes that the new methods are efficient for all manufacturing nodes and especially for deep nanometer ranges. The technology enables the manufacturing of more transistors on a silicon wafer in order to place more circuits/features on a die. The new manufacturing architecture enables larger designs within smaller areas and significantly increases the silicon yield. The invention supports analog, RF, digital, MIXED and MEMS designs. We believe that it has the potential to revolutionize integrated circuits manufacturing and packaging, enabling huge chips on affordable silicon areas. It may be especially significant when it comes to heavily area-dependent ICs, for example memory chips, MEMS (Micro-Electro-Mechanical Systems) and micro solar cells.
(0)
(0)Scroll down for more posts ▼