$GTCH an update to its press release from October 29, 2020, that its 3D microchip patent received a grant date as of December 1, 2020 by the United States Patent and Trademark Office (“USPTO”); U.S. Patent No. 10,854,763. The Company filed for this patent on March 5, 2019.
The invention relates to the field of integrated circuit (IC) silicon structure, and more particularly to multi-dimensional, multi-planar microchips. This patent covers GBT's futuristic integrated circuit technology which introduces new methods for microchip's manufacturing. The concept presents a new die structure and orientation. The Company believes that the new methods are efficient for all manufacturing nodes and especially for deep nanometer ranges. The technology enables the manufacturing of more transistors on a silicon wafer in order to place more circuits/features on a die. The new manufacturing architecture enables larger designs within smaller areas and significantly increases the silicon yield. The invention supports analog, RF, digital, MIXED and MEMS designs. We believe that it has the potential to revolutionize integrated circuits manufacturing and packaging, enabling huge chips on affordable silicon areas. It may be especially significant when it comes to heavily area-dependent ICs, for example memory chips, MEMS (Micro-Electro-Mechanical Systems) and micro solar cells.
When it comes to these types of microchips, silicon area is crucial and every micron is important. The new approach will enable the manufacturing of much larger chips within affordable areas. A three-dimensional integrated circuit is a metal-oxide semiconductor (MOS) integrated circuit, manufactured by stacking silicon dies and electrically interconnecting them vertically. GBT's invention goes beyond 3D concept with multi-plane silicon structures, for example honeycomb, hexagonal and further multi-planetary structures, with the goal of increasing silicon surface area. The patent covers silicon interconnection not only vertically but in a multi planar way which opens an entire world of possibilities maximizing silicon area. Manufacturing these types of structures will enable the design of chips with multi-trillion transistors on die, creating new horizons for our entire electronics world. Few examples of areas that will be significantly enhanced are flash memories, GPUs, CPUs, displays, micro-solar cells panels, RF, and MEMS.
"We are glad to announce that we will be granted our multi-planer microchip patent on December 1, 2020," said Danny Rittman, GBT’s CTO. "By manufacturing honeycomb, hexagonal and other multi planer structural shapes die, we believe IC design houses will be able to increase their silicon surface for transistors. Especially when it comes to memory circuits, silicon real-estate is a key factor. As more we can place on the silicon, as better, given reasonable, affordable die size. We believe the invention will enable to design and manufacture gigantic chips for all design processes including advanced nodes like 10nm, 7nm, 5nm and below."
The invention relates to the field of integrated circuit (IC) silicon structure, and more particularly to multi-dimensional, multi-planar microchips. This patent covers GBT's futuristic integrated circuit technology which introduces new methods for microchip's manufacturing. The concept presents a new die structure and orientation. The Company believes that the new methods are efficient for all manufacturing nodes and especially for deep nanometer ranges. The technology enables the manufacturing of more transistors on a silicon wafer in order to place more circuits/features on a die. The new manufacturing architecture enables larger designs within smaller areas and significantly increases the silicon yield. The invention supports analog, RF, digital, MIXED and MEMS designs. We believe that it has the potential to revolutionize integrated circuits manufacturing and packaging, enabling huge chips on affordable silicon areas. It may be especially significant when it comes to heavily area-dependent ICs, for example memory chips, MEMS (Micro-Electro-Mechanical Systems) and micro solar cells.
When it comes to these types of microchips, silicon area is crucial and every micron is important. The new approach will enable the manufacturing of much larger chips within affordable areas. A three-dimensional integrated circuit is a metal-oxide semiconductor (MOS) integrated circuit, manufactured by stacking silicon dies and electrically interconnecting them vertically. GBT's invention goes beyond 3D concept with multi-plane silicon structures, for example honeycomb, hexagonal and further multi-planetary structures, with the goal of increasing silicon surface area. The patent covers silicon interconnection not only vertically but in a multi planar way which opens an entire world of possibilities maximizing silicon area. Manufacturing these types of structures will enable the design of chips with multi-trillion transistors on die, creating new horizons for our entire electronics world. Few examples of areas that will be significantly enhanced are flash memories, GPUs, CPUs, displays, micro-solar cells panels, RF, and MEMS.
"We are glad to announce that we will be granted our multi-planer microchip patent on December 1, 2020," said Danny Rittman, GBT’s CTO. "By manufacturing honeycomb, hexagonal and other multi planer structural shapes die, we believe IC design houses will be able to increase their silicon surface for transistors. Especially when it comes to memory circuits, silicon real-estate is a key factor. As more we can place on the silicon, as better, given reasonable, affordable die size. We believe the invention will enable to design and manufacture gigantic chips for all design processes including advanced nodes like 10nm, 7nm, 5nm and below."
