$GTCH news alert! Oct. 29, 2020 (GLOBE NEWSWIRE) -
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Posted On: 11/04/2020 6:32:57 AM
$GTCH news alert! Oct. 29, 2020 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT”, or the “Company”), announced that it received a notice of allowance for application number 16/292,388, which was filed on March 5, 2019, issued by the United States Patent and Trademark Office (“USPTO”) for its 3D, Monolithic, multi-dimensional, multi-plane, memory structure for integrated circuits patent. The application has been examined by USPTO and is allowed for issuance as a patent. The Company expects that it will receive a granted date during the next few months.
The present invention relates to the field of integrated circuit (IC), and more particularly to multi-dimensional, multi-planar IC memory. GBT's 3D microchip patent is protecting GBT's futuristic integrated circuit technology which introduces new systems and methods for microchip's manufacturing. The invention is designed to present a new die structure and orientation with a focus on deep nanometer range. The goal of the technology is to enable manufacturing more devices on silicon in order to achieve more circuits/features on die. Further, it is designed to enables new IC architectures for larger designs within smaller areas while lowering the overall IC's power consumption. This target market for this technology, when fully developed, will be area-dependent ICs such as memory chips, MEMS (Micro-Electro Mechanical Systems) and micro solar cells.
The present invention relates to the field of integrated circuit (IC), and more particularly to multi-dimensional, multi-planar IC memory. GBT's 3D microchip patent is protecting GBT's futuristic integrated circuit technology which introduces new systems and methods for microchip's manufacturing. The invention is designed to present a new die structure and orientation with a focus on deep nanometer range. The goal of the technology is to enable manufacturing more devices on silicon in order to achieve more circuits/features on die. Further, it is designed to enables new IC architectures for larger designs within smaller areas while lowering the overall IC's power consumption. This target market for this technology, when fully developed, will be area-dependent ICs such as memory chips, MEMS (Micro-Electro Mechanical Systems) and micro solar cells.
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