the Ayer/Intel presentation reinforces the pervasive need for LWLG's incredible P2IC Platform technology, from the slides,
Putting it together: First CPU with optical I/O
C. Sun, M. Wade, et al., Nature 2015
• Single SOI CMOS CPU
chip with optical I/O
• 70M transistors
• ~1,000 optical devices
• Microring based WDM
https://ayarlabs.com/download/teraphy-a-chipl...tical-i-o/
Ok folks, now put on your thinking caps and remember what Rockley Photonics CEO Andrew Rickman told us,
Rickman also argued that despite any hype to the contrary, silicon photonics is not compatible with advanced CMOS nodes, because of the properties of light. “Most companies building silicon photonics chipsets come from a microelectronics legacy based on an old but still unproven strategy to leverage existing silicon CMOS foundries and processes,” he said. “The problem is that photons and electrons have vastly different behaviors and, therefore, CMOS nodes optimized for electrons are not necessarily the best choice for highly optimized photonics circuits.”
There are several resulting practical considerations. Silicon photonics requires an SOI CMOS process, which is not available at the same advanced nodes as standard CMOS, and certain processing steps are required that are not available in the standard process flow. Also, for a high-speed modulator to work in silicon, the waveguide must shrink to submicron sizes, much smaller than the wavelength of the light passing through it. At these tiny geometries, the propagation losses increase and efficiency decreases.
https://investorshub.advfn.com/boards/read_ms...=150147634
So they have a BIG BIG PROBLEM
Now enter LWLG !!
LWLG is perfectly positioned to exploit co-packaging!
ASM Q&A at about 1:01:01 Dr Lebby talks about how LWLG's technology is perfectly positioned for the Photonics Industry's rapid trend towards CO-PACKAGING
https://www.youtube.com/watch?v=N1ppBSAPrHg&a...e=youtu.be
Listen to what Dr Lebby's said, "co-packaging is where you bring the optics right next to the electronic chip, the CMOS chip, in fact, you put it actually on the chip, so you want to make that inter-connect as short as you can, so that the interaction between the electronics and the photonics is as close as possible, and if you think about our technology for a second, we've got a spin-on polymer technology that you can spin on to IC's and CMOS, so we are ideally positioned to harness the co-packaging trend that is occurring, so yes, I am watching the competition in terms of the materials and the performance of the devices, but we're also watching how it gets packaged together, and we are actually ideally positioned for this new trend that's just occurring where other technologies are going to suffer , and so yes it's not just the materials, it's not just the device's but you have to look at the packaging too, and you have to look at where all the fronts are, and where the technologies are progressing and at what rate, and the conclusion is that mother nature is working with us on a number of different fronts, and that's really really exciting!"
Putting it together: First CPU with optical I/O
C. Sun, M. Wade, et al., Nature 2015
• Single SOI CMOS CPU
chip with optical I/O
• 70M transistors
• ~1,000 optical devices
• Microring based WDM
https://ayarlabs.com/download/teraphy-a-chipl...tical-i-o/
Ok folks, now put on your thinking caps and remember what Rockley Photonics CEO Andrew Rickman told us,
Rickman also argued that despite any hype to the contrary, silicon photonics is not compatible with advanced CMOS nodes, because of the properties of light. “Most companies building silicon photonics chipsets come from a microelectronics legacy based on an old but still unproven strategy to leverage existing silicon CMOS foundries and processes,” he said. “The problem is that photons and electrons have vastly different behaviors and, therefore, CMOS nodes optimized for electrons are not necessarily the best choice for highly optimized photonics circuits.”
There are several resulting practical considerations. Silicon photonics requires an SOI CMOS process, which is not available at the same advanced nodes as standard CMOS, and certain processing steps are required that are not available in the standard process flow. Also, for a high-speed modulator to work in silicon, the waveguide must shrink to submicron sizes, much smaller than the wavelength of the light passing through it. At these tiny geometries, the propagation losses increase and efficiency decreases.
https://investorshub.advfn.com/boards/read_ms...=150147634
So they have a BIG BIG PROBLEM
Now enter LWLG !!
LWLG is perfectly positioned to exploit co-packaging!
ASM Q&A at about 1:01:01 Dr Lebby talks about how LWLG's technology is perfectly positioned for the Photonics Industry's rapid trend towards CO-PACKAGING
https://www.youtube.com/watch?v=N1ppBSAPrHg&a...e=youtu.be
Listen to what Dr Lebby's said, "co-packaging is where you bring the optics right next to the electronic chip, the CMOS chip, in fact, you put it actually on the chip, so you want to make that inter-connect as short as you can, so that the interaction between the electronics and the photonics is as close as possible, and if you think about our technology for a second, we've got a spin-on polymer technology that you can spin on to IC's and CMOS, so we are ideally positioned to harness the co-packaging trend that is occurring, so yes, I am watching the competition in terms of the materials and the performance of the devices, but we're also watching how it gets packaged together, and we are actually ideally positioned for this new trend that's just occurring where other technologies are going to suffer , and so yes it's not just the materials, it's not just the device's but you have to look at the packaging too, and you have to look at where all the fronts are, and where the technologies are progressing and at what rate, and the conclusion is that mother nature is working with us on a number of different fronts, and that's really really exciting!"
