$POET (copy) is keeping 100% of their OI technolog
Post# of 1140
The dielectric waveguides and the connectivity associated with the Optical Interposer offers a level of advantage that make it a step change. Everything has been built around the dielectric waveguides.
I expect that there will be an awakening when it is revealed who the new owner of DensLight is and it may set off a chain of events where global companies sees the new owner as having a big advantage in being part of the optical engine supply chain for not just their own products but potentially products of competing companies? Not sure how that will be resolved. I believe the primary financial needs right now by POET is to finance production orders which in turn benifits the new owner ether directly for their own optical engine or indirectly to supply optical engines for others. I expect that the $4 million earn out may be associated with POET being at a stage of readiness to supply orders.
So lets do a partial comparison to why companies want to use the POET Optical Interposer platform in part or in whole. Below are POETs dielectric waveguide metrics for transmission and insertion loss.
<0.5dB/cm Transmission Loss – minimal impact of surface roughness
<0.5dB coupling loss to SMF with appropriate waveguide design
POET blows away the competition with those numbers.
Let’s look at the leading platforms today sourced from a report prepared by by Ayar Labs principals May 2018:
Non-monolithic:
IMEC
Availability: prototyping/research
Integration method: wire bond
Waveguide loss: 1 dB/cm
Couplers loss: 2 dB
HP
Availability: prototyping/research
Integration method: wire bond
Waveguide loss: 3 dB/cm
Couplers loss: 5 dB
Luxtera/TSMC
Availability: high volume (assumes 300mm foundry)
Integration method: 3D cu-pillar
Waveguide loss: 1.9 dB/cm
Couplers loss: 2.2 dB
ST Microelectronics
Availability: high volume
Integration method: 3D cu-pillar
Waveguide loss: 3 dB/cm
Couplers loss: 2.15 dB
Monolithic type SiPh
Ayar Labs 45nm SOI CMOS
Availability: high volume
Waveguide loss: 3.7 dB/cm - Note the very the high signal loss assumed as a result of using the smallest node at 45nm to facilitate processor circuits.
Couplers loss: 1.5 dB (2.5 dB pigtailed)
PD bandwidth is 5GHz….ouch. Compare this for example to IMEC’s non monolythic solution at 50GHz
Luxtera 130 nm SOI CMOS
Availability: medium volume
Waveguide loss: 1 dB/cm
Couplers loss: 1.5 dB
IBM (now GF) 90 nm SOI CMOS
Availability: high volume
Waveguide loss: 2.5 dB/cm
Couplers loss: 2.5 dB
HP 250 nm SOI CMOS
Availability: medium volume
Waveguide loss: 2.4 dB/cm
Couplers loss: 1.5 dB
Oracle 130 nm SOI CMOS
Availability: medium volume
Waveguide loss: 3 dB/cm
Couplers loss: 5.5 dB
Below are some interesting facts related to the efforts to add photonics and electronics into mixed signal silicon. Keep in mind that additional barriers associated with silicon photonics is the inability to produce a suitable light source in silicon and the battle to control temperature requirements for wavelength control on a common silicon die.
Being able to create passive photonic devices in silicon, as well as affect the index of refraction through some current or voltage controlled mechanism are the necessary steps towards creating optical coupling, guiding and modulating devices for photonic interconnects. However, the other key pieces of technology are the photodetector and the approach for integration with electronics, which determine the effectiveness of photon-electron conversion, and ultimately the energy cost, speed, and bandwidth-density and integration cost of the overall solution
The first commercial high-volume process, developed by Luxtera, attempted to address all of the issues above at the same time, by integrating the photonic devices in a then state-of-the-art 130nm silicon-on-insulator (SOI) CMOS process [2]. To yield good photonic device performance the process had to be modified with epitaxial Ge step for efficient photodetectors, as well as Si body partial-etch for passive and active waveguide structures. Small parasitic capacitances between transistors and devices were realized through monolithic integration, enabling energy-efficient, high-bandwidth transmitter and receiver components. However, the process customizations and economic investment that led to having the improved photonic device performance, also prevented the technology from following the CMOS scaling trends of shrinking the device features every two years, and hence improving the transistor and system speed and energy-efficiency. Furthermore, since interconnect speeds are scaling at an even faster rate of 4× every two years, this meant that the technology would soon fail to deliver the speeds required in new interconnect standards.
It has been challenging for this technology to achieve 25 Gb/s modulation even into relatively small photonic loads such as ring-based optical modulators [3]. To make a major impact, every process technology has to be qualified and available for high-volume production, and every additional process step complicates and slows down this process, further preventing the technology from following the mainstream scaling trends. Similarly, IBM’s monolithic photonic platform [4], which was implemented in a more advanced 90 nm node, took several years to qualify and achieve high-volume and availability due to process customizations.
snagged from agoracom https://agoracom.com/ir/POETTechnologies/foru...72#message
nice to have some comparisons to technologies Poet OI will compete
- proro