MILPITAS, CA --(Marketwired - October 10, 2016) - Open-Silicon, a system-optimized ASIC solution provider, will present on overcoming the challenges associated with assembly implementation of ultra-thin profile flipchip package-on-package at the IMAPS 49 th Annual International Symposium on Microelectronics in Pasadena, CA. IMAPS 2016 is a production of the International Microelectronics Assembly and Packaging Society. This year's theme is "Packaging the Connected World."
Presentation: "Challenges in Assembly Implementation of Ultra-Thin Profile Flipchip Package-on-Package"
Presenter: Abu Eghan, Senior Manager, Assembly & Packaging, Open-Silicon
When/Where: Thursday, October 13 from 1:00 p.m. - 1:25 p.m. - Advanced Packaging & Enabling Technologies Track - Ballroom C - Pasadena Convention Center
Presentation Abstract:
This presentation will address the assembly and structural challenges associated with a low profile bare die flipchip Package-on-Package (PoP), and will outline a case study where process optimization steps and trade-offs were used to achieve success through assembly. The PoP was designed to accommodate a JEDEC 256-ball FBGA memory. This dual channel 32-bit LPDDR3 memory package has a unique signal crossing ball arrangement between the data bus of one channel and the control/address (CAS) bus of the other. The ball arrangement presents some crossing challenges for PoP implementation of controller ICs. For timing reasons, the memory controller blocks are traditionally placed together in a central area of the base chip, and signals are routed to line up with the fixed LPDDR3 landing sites. For this dual channel case, the routing required crossing one CAS signal group over the data lines of the other. To address this crossing, a copper redistribution layer (RDL) was deployed at the bump stage to bring the appropriate LPDDR3 signals from the controller block to line up with the memory balls. The thick copper RDL/Cu-pillar arrangement left a 10-13um of dielectric layer over the base die. Because of the 0.4mm pitch and clearance requirements of the selected memory package, a very low profile flipchip die standoff was required. The dielectric layers and copper density in RDL had significant impact on the handling of these thinned wafers and die through the assembly processes. Although newer package offerings, like Amkor's Thru Mold Via (TMV) technology or Invensas' Bond Via Array (BVA), could have been deployed, a Cu-pillar based bare die flipchip (FCBGA) using a very thin die was selected for its simplicity and lower cost. All package related reliability tests have been completed, and the solution is currently shipping in volume production.
About Open-Silicon Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers' products by innovating at every stage of design -- architecture, logic, physical, system, software and IP -- and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed over 300 designs and shipped over 120 million ASICs to date. Privately-held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com
Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.
Contact Information: Purvi Shenoy Open-Silicon 408-240-5772 Email contact Media Contact: Jennifer DeAnda 208-794-7113 Email contact
