OTTAWA, ON--(Marketwired - August 23, 2016) - Sidense Corp., a leading developer of Non-Volatile Memory (NVM) One-Time Programmable (OTP) IP cores, today announced that it has demonstrated successful operation of its patented SHF 1T-OTP memory macros at TSMC's 16FF+ and 16FFC process nodes.
Parametric measurements for both 16FF+ and 16FFC silicon were made during programming and read operations, and at-speed tests have been run on four macros totaling 4 Mbits of memory. Split lots are being characterized across the entire operating range. Qualification will follow Sidense standard procedures for HTOL and HTS reliability testing and will conform to the automotive standard AEC-Q100 Grade 1 (125°C). Customer design kits, supporting a range of configurations, will be made available early next quarter. Fully qualified Sidense 1T-OTP macros will be available to customers in 1Q17 (16FF+) and 2Q17 (16FFC).
"Our highly secure and reliable split-channel 1T-OTP bit cell, the heart of all our OTP products, shows superior performance characteristics as we scale down to 16nm and smaller geometry FinFET structures," said Ken Wagner, Sidense Senior Vice President of Engineering. "Our upcoming OTP macros for TSMC's 16FFC and 16FF+ process nodes will enable our customers to develop leading-edge products targeting the IoT, mobile computing, communications and automotive markets."
For 16nm implementation, Sidense is adding several enhancements to its proven SHF 1T-OTP architecture including low-voltage reads along with a differential read mode and enhanced security features, such as improved side-channel attack and tamper protection features. When implemented in TSMC's 16nm processes, Sidense's 1T-OTP FinFET bit cell shows a significant area reduction compared to TSMC 20SOC implementation, more than 10 times lower leakage currents than 28nm/20nm bit cells, higher programmed cell current and five orders of magnitude difference in read current between programmed and un-programmed states.
About TSMC 16FFC and 16FF+ Processes
16FFC is a "compact" version of TSMC's 16FF+ process. ICs fabricated in the 16FFC process may be used in ultra-low-power applications such as wearables and IoT applications. Compared to 28HPC+, both 16FF+ and 16FFC provide more than 40% speed improvement, and more than 80% leakage reduction. By leveraging the experience of 20SoC technology, TSMC 16FF+ shares the same metal backend process in order to quickly improve yield and demonstrate process maturity for accelerating product time-to-market.
About SHF Memory IP
Sidense SHF One-Time-Programmable (OTP) memory IP is based on a patented 1T-Fuse™ (anti-fuse) bit-cell. The 1T-Fuse bit-cell uses gate oxide breakdown as a robust, non-reversible programming mechanism. Optimized for high-performance and a wide range of bit densities, Sidense SHF macros are available for standard CMOS processes. There are no requirements for any additional masks or processing steps.
Sidense SHF memory IP is provided as a complete, non-volatile memory (NVM) subsystem providing interfaces and features to support a range of embedded SoC applications. The SHF module integrates the OTP memory and Integrated Power Supply (IPS) hard macro blocks along with program control, programming and test interface, error correction and Built-In Self-Test (BIST) RTL. SHF applications include: code storage, ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration.
About Sidense Corp.
Sidense Corp. provides very dense, highly reliable and secure non-volatile one-time programmable (OTP) Logic Non-Volatile Memory (LNVM) IP for use in standard-logic CMOS processes. The Company, with over 120 patents granted or pending, licenses OTP memory IP based on its innovative one-transistor 1T-Fuse™ bit cell, which does not require extra masks or process steps to manufacture. Sidense 1T-OTP macros provide a better field-programmable, reliable and cost-effective solution than flash, mask ROM, eFuse and other embedded and off-chip NVM technologies for many code storage, encryption key, analog trimming and device configuration uses.
Over 150 companies, including many of the top fabless semiconductor manufacturers and IDMs, have adopted Sidense 1T-OTP as their NVM solution for more than 500 designs. Customers are realizing outstanding savings in solution cost and power consumption along with better security and reliability for applications ranging from mobile and consumer devices to high-temperature, high-reliability automotive and industrial electronics. The IP is offered at and supported by all top-tier semiconductor foundries and selected IDMs. Sidense is headquartered in Ottawa, Canada with sales offices worldwide. For more information, please visit www.sidense.com.
Media Contacts:
Susan Cain
Cain Communications for Sidense
Tel: 408-393-4794
Email: scain@caincom.com
Jim Lipman
Sidense
Tel: 925-606-1370
Email: jim@sidense.com
