The following SBIR is a phase 2 with the Navy for $750k . It started mid April 2010 and the end date is June 16, 2012.
The Abstract of this SBIR “Optoelectronic directional couplers for optical switching fabrics”
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Abstract: |
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Phase II Interim
Summation
All-Optical-Switching for nearly 30 years has been identified as a necessary capability for the routing of high speed optical data. Yet little progress has been made towards a commercial implementation and even now recent comparisons of optical and electronic packet switching in terms of scalability and energy consumption conclude that optical packet switches do not appear to offer significant improvements or energy savings compared to electronic ones. This position states that the key impediment to scaling optical switch fabrics is the energy consumed in the electronic circuits that drive the individual optical devices in the fabric and the energy consumed by the network of control lines that feed these drivers. The optical device technologies previously considered are the AWG based switches, SOA arrays, electro-optic phased-array switches and micro-resonator switches.
In this effort, we develop POET as an alternative optical switch approach that solves these problems . POET also uses micro-resonator based switches but electronic drivers are not required because the switch is a thyristor with unique properties. First the switch has a built-in calibration mechanism so that a driver circuit is not required to adjust and maintain the resonant frequency. Second, the thyristor has the latching (memory) property so that drive signals are not required to maintain each individual element. Third when the fabric is designed as a memory array the packets may be passed in a power down mode in which the array power is minimal. Finally, the POET approach allows a merging of the optical and electronic planes of the router and thus eliminates many of the EO and OE converters required for packet header recognition and replacement. When these converters are required, they are simple single stage circuits consuming minimal power.
ODIS has made significant progress in designing the appropriate resonator geometry for operation in the 1µm region, which includes the appropriate waveguide interconnect structure, the electrode structure for control of the memory and the internal cell resistor. Dynamic simulations have shown the fabric to be capable of passing 40Gb/s digital data as well as 40GHz RF. ODIS has also determined how to use the optical bit pattern in the header of the packet to perform the writing operation which simplifies the instructions required from the electronic plane. The basic cell consists of 2 optically coupled thyristor resonators coupling to input and output waveguides using minimum sized devices of 5µm on a side. Thyristor switching places the devices into the through or cross state which realizes the basic 2 x 2 functionality. WDM operation is easily accommodated by providing parallel paths at each element designed for another wavelength. Experimentally, ODIS has designed the photomasks to demonstrate the basic cell operation as well as the compatibility with the basic transistor operations inherent to the POET epitaxy. Much of the process development for this part of the work (to optimize the process producing both thyristors and transistors) has been performed to enable technology transition to BAE systems. The transition is on track with 1st reported nFET bandwidths of 38.6GHz.
Anticipated Benefits
The commercial market opportunity for optical switching fabrics could be significant if the POET optical switch becomes a serious contender for the electronic switching approach. This is expected to happen around 40GB/s data stream rates since the POET cHFET VLSI capability will dramatically outperform CMOS when the feature size gets to 0.1µm. However optical fabrics are only one aspect of one vertical market. There are numerous other vertical markets which POET will dominate and these include the wireless and handheld markets, semiconductor memory market, the server market and the general microprocessor markets to name a few. POET, with OE capability will then become a mainstream technology for all markets for data rates above 40GB/s
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Some comments from Dr Taylor on this and the ultra low power memory is contained in the following article from Semiconductor Today
