2nd amendment to the 20F.
http://www.sec.gov/Archives/edgar/data/143742...fr12ga.htm
New paragraphs are:
""The Company has designed POET to be relatively easy to implement utilizing industry standard tools and infrastructure. The ability to utilize industry standard circuit design tools and process flows enables low adoption cost for the implementation of POET. The POET wafer fabrication process is similar to that for current industry standard silicon CMOS, as POET supports current manufacturing and testing infrastructures, including test-on-wafer techniques, as well as post-fabrication procedures comparable to existing silicon CMOS procedures. The primary additional requirement for silicon CMOS foundries would involve the acquisition of molecular beam epitaxy (“MBE”) capability for the pre-processed GaAs wafers, or outsourcing the purchase of such wafers.""
"The Company seeks to monetize its technology assets by a combination of (i) license revenues for specific vertical markets, with grants of exclusive rights for agreed upon timeframes; (ii) foundry non-recurring engineering (“NRE”) revenues for POET technology transfer and support to foundries adding POET capability to their product and services offerings; (iii) foundry design kit royalty revenues from sales by foundries of libraries and designs kits incorporating POET to device designers developing new chip offerings; and (iv) royalties from sales by integrated circuit manufacturers and OEMs of POET chips sold individually or incorporated into an electronic device. The Company is targeting initial revenues from NRE to begin within twelve months of the date of this Registration Statement. In support of its marketing efforts, the Company is developing working prototypes of certain devices — ring oscillator and high-speed vertical cavity laser — in order to display the capabilities of POET. The Company projects that such prototypes will be ready for display and testing by the end of 2014."
new wording to emphasize that PET is also important: ... "In addition, the POET technology encompasses the ability to incorporate positive and negative heterostructure field effect transistors (“HFETs”) on a single GaAs wafer, thus substantially broadening the capabilities of a GaAs semiconductor device, as well as positive and negative heterojunction bipolar transistors (“HBTs”) on a single GaAs wafer, allowing for much greater power efficiency and speed, as well as the incorporation of analog and digital circuits in a single chip design."
May 15 20F filing:
The Company expects that the First Phase of commercialization will generate non-recurring engineering revenue with partners, foundries or both with an initial prototype device anticipated to be available by Q4 2014 into Q1 2015
June 12 20F filing:
The Company expects that the First Phase of commercialization will generate non-recurring engineering revenue with OEMs, foundries or both with an initial prototype device anticipated to be available by the end of 2014.
http://www.sec.gov/Archives/edgar/data/143742...fr12ga.htm
New paragraphs are:
""The Company has designed POET to be relatively easy to implement utilizing industry standard tools and infrastructure. The ability to utilize industry standard circuit design tools and process flows enables low adoption cost for the implementation of POET. The POET wafer fabrication process is similar to that for current industry standard silicon CMOS, as POET supports current manufacturing and testing infrastructures, including test-on-wafer techniques, as well as post-fabrication procedures comparable to existing silicon CMOS procedures. The primary additional requirement for silicon CMOS foundries would involve the acquisition of molecular beam epitaxy (“MBE”) capability for the pre-processed GaAs wafers, or outsourcing the purchase of such wafers.""
"The Company seeks to monetize its technology assets by a combination of (i) license revenues for specific vertical markets, with grants of exclusive rights for agreed upon timeframes; (ii) foundry non-recurring engineering (“NRE”) revenues for POET technology transfer and support to foundries adding POET capability to their product and services offerings; (iii) foundry design kit royalty revenues from sales by foundries of libraries and designs kits incorporating POET to device designers developing new chip offerings; and (iv) royalties from sales by integrated circuit manufacturers and OEMs of POET chips sold individually or incorporated into an electronic device. The Company is targeting initial revenues from NRE to begin within twelve months of the date of this Registration Statement. In support of its marketing efforts, the Company is developing working prototypes of certain devices — ring oscillator and high-speed vertical cavity laser — in order to display the capabilities of POET. The Company projects that such prototypes will be ready for display and testing by the end of 2014."
new wording to emphasize that PET is also important: ... "In addition, the POET technology encompasses the ability to incorporate positive and negative heterostructure field effect transistors (“HFETs”) on a single GaAs wafer, thus substantially broadening the capabilities of a GaAs semiconductor device, as well as positive and negative heterojunction bipolar transistors (“HBTs”) on a single GaAs wafer, allowing for much greater power efficiency and speed, as well as the incorporation of analog and digital circuits in a single chip design."
May 15 20F filing:
The Company expects that the First Phase of commercialization will generate non-recurring engineering revenue with partners, foundries or both with an initial prototype device anticipated to be available by Q4 2014 into Q1 2015
June 12 20F filing:
The Company expects that the First Phase of commercialization will generate non-recurring engineering revenue with OEMs, foundries or both with an initial prototype device anticipated to be available by the end of 2014.
