$GTCH GBT’s visual, design rule detection and correction program is operating on an IC layout database, identifying violations, and performing the necessary correction, ensuring a correct-by-construction IC design environment. This approach could save significant amount of the global project’s design time by early identification and elimination of design’s violations and flaws. GBT believes that by adding GAA FET support, design time could be reduced especially with advanced upcoming nanometer chips of 2nm and beyond. GBT plans to incorporate GAA FET support within all its EDA software tools in order to remain at the forefront of the IC design arena.