$GTCH The main goal of the compaction process is to create the densest IC layout possible. GBT is now designing an AI empowered technology to read existing and new microchip’s layout data with the goal of producing the densest layout block possible. The technology is seeking to optimize post-layout IPs, shrinking them automatically retaining geometrical design rule and electrical connectivity correctness. In addition, a goal of the computer program is to maintain Design for Manufacturing (DFM) constraints to comply with the manufacturing process. The technology design contemplates implementing graph-based optimization algorithms and deep learning training for fast processing and optimal area utilization.

https://seekingalpha.com/pr/18671571-gbt-seek...ed-circuit