$GTCH the semiconductor field is pushing the envelope by introducing smaller manufacturing processes scaling into deep nanometer ranges. Scaling down the manufacturing process enables billions of transistors on die, higher performance, and power consumption reduction, but introduces new design challenges due to complicated physics rules. IC projects may take longer time as they need to comply with a vast amount of complex design rules and constraints. It is the Company’s position that an automatic IC layout compaction technology can be an efficient way to reduce new and existing layout IPs size utilizing less silicon area with the goal of increasing the overall yield.

The main goal of the compaction process is to create the densest IC layout possible. GBT is now designing an AI empowered technology to read existing and new microchip’s layout data with the goal of producing the densest layout block possible. The technology is seeking to optimize post-layout IPs, shrinking them automatically retaining geometrical design rule and electrical connectivity correctness. In addition, a goal of the computer program is to maintain Design for Manufacturing (DFM) constraints to comply with the manufacturing process. The technology design contemplates implementing graph-based optimization algorithms and deep learning training for fast processing and optimal area utilization.

The technology is targeted for Analog, Digital, RF and MIXED integrated circuits styles with the goal of supporting GDSII and Oasis data.