$GTCH scaling down the manufacturing process enables billions of transistors on die, higher performance, and power consumption reduction, but introduces new design challenges due to complicated physics rules. IC projects may take longer time as they need to comply with a vast amount of complex design rules and constraints. It is the Company’s position that an automatic IC layout compaction technology can be an efficient way to reduce new and existing layout IPs size utilizing less silicon area with the goal of increasing the overall yield.