$GTCH GBT is now designing a new EDA software tool to automatically generate integrated circuits layout IP blocks. The tool will read process design rules, constraints, and detailed system specifications and automatically generate an IP layout block. The primary technology’s goal is to reduce an IC project’s design and costs, as well as, the silicon space occupied by large systems. An efficient SoC design consumes low power, offering high performance, within a smaller physical space. Using automatic IP block generator will enable faster and cheaper SoC’s design, making it possible to create a world of intelligent electronic devices in wide variety of domains.

https://www.nasdaq.com/press-release/gbt-is-d...d-circuits