$GTCH from their news: "We are now designing an EDA software tool for automatic generation of IP layout blocks that can be reused unlimited times across SOC designs. For example, a microprocessor chip includes a wide variety of sub-systems for functionalities that can be standardized as IP blocks. The technology is manufacturing process aware to support older and advanced nanometer processes, making it a flexible tool for IC design firms. As Integrated Circuits technology advances, more functionalities, lower power consumption, higher performance and lower cost are in high demand, especially with advanced nanometer projects. An automatic IP layout block generator will offer the capability to create the necessary sub-systems at a very short time, enabling much faster and cheaper IC projects designs. Ultimately it will majorly reduce project’s time-to-market, design efforts and cost, creating a whole world of IC designs possibilities,” stated Danny Rittman, the Company’s CTO.