$GTCH The invention includes a method and system for automatic correction of an IC layout design rule violations to match the process rule deck reference. The automatic correction, once implemented maintains the integrated circuit mask layout electrical connectivity (LVS), reliability (RV) and Design for Manufacturing (DFM) correctness. The number of design rules has been dramatically increased over the years especially in advanced nanometer process of 7nm and below. In addition, geometrical design rules became more convoluted and highly complex to comply which requires vast amount of manual correction. Using the invention once fully developed, GBT predicts a significant IC layout productivity enhancement, enabling higher silicon yield and faster microchip’s time to market. Fabless IC design firms will be able to design and manufacture their chips faster and with lower cost.

https://www.nasdaq.com/press-release/gbt-file...sign-rules