$GTCH Delta is seeking to automate this process using deep learning technology for specification-driven IC layout blocks porting. The computer program will be migrating from one process to another ensuring the IC’s layout adheres to all advanced design rules, including deep nanometer support like double patterning. The Delta research will seek to take into consideration the new process electrical and reliability constraints and optimize the data composite rules. Delta is also seeking to perform automatic, multi-dimensional, dynamic layout compaction to minimize the overall chip’s area and increase silicon yield. The data compaction will correct all layout design rules, including complex reliability verification (RV), and DFM (Design for Manufacturing) rules for advanced process.

https://www.bloomberg.com/press-releases/2021...technology