$GTCH The EDA R&D efforts will be concentrating on DFM rules analysis, physical layout geometrical rules (DRC) and nanometer silicon modeling. The planned solution will be a real-time, interactive guiding system with the goal of enabling DFM advice/auto-correction early during the microchip’s design stage. GBT already started to address a key dependency between manufacturing and IC design; the Design Rule Check (DRC) aspect. IC DRC rules are geometrical design constraints, imposed by the manufacturing process. These constraints are enforced due to manufacturing process limitations and typically required long design time to achieve compliance. The new approach will target to embed DFM manufacturing rules along with geometrical rules check (DRC) to advise designers with the goal of making their IC design more compatible for manufacturing. The goal is to increase silicon yield, obeying to power and performance constraints, through early adherence of DFM rules, rather than complying only with DRC rules.