$GTCH The goal of the new manufacturing architecture is to enable larger designs within smaller areas and, in turn, providing for increases in the silicon yield to enhance surface area, especially for smaller nodes like 5nm, 3nm and below.

GBT is aiming to protect its 3D, multiplanar chip intellectual property in key countries and continents. The invention is designed to present a new die structure and orientation with a focus on deep nanometer range. The IP is especially efficient for memory chips since it describes a new way to design and manufacture enormous size memory integrated circuits and fits analog, digital, and mixed signal type ICs. The patent contemplates placing more circuits on silicon within small areas, which is expected to enable sophisticated chips particularly with memories, CPU, GPU and more. The method contemplated by the patent application enables lowering the overall IC's power consumption and increasing its performance. The company’s 3D microchip patent was filed on March 5, 2019 and was granted as of December 1, 2020 by the United States Patent and Trademark Office (“USPTO”); U.S. Patent No. 10,854,763.