$GTCH VeriSpeed research project introduces a new approach to this essential element in this process, the IC’s data reading. By applying intelligent algorithms, the program will read the huge data according to a specific algorithm flow substantially speeding the entire verification process of nanometer and other Integrated Circuit’s layout Designs thus significantly impacting the global project’s design time cycle and manufacturing efficiency. The project aims to accelerate the entire IC’s verification process to enable reduction of total Integrated Circuit design time. This new database engine approach is targeted to work with GBT’s multiplanar methods as presented in the recent granted patent.

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