Alchip Technologies Advances 3DIC Ecosystem with Test Chip Results
Alchip Technologies Advances 3DIC Ecosystem with Test Chip Results
Alchip Technologies, a key player in high-performance ASIC solutions, recently demonstrated its leadership in 3DIC technologies through successful outcomes from its test chip tape-out. This milestone showcases the comprehensive readiness of Alchip's 3DIC ecosystem, validating multiple components integral to advanced chip development.
The test chip serves as an important landmark, showcasing Alchip's 3DIC technology which integrates an entire solution that includes CPU and NPU core demonstrations, and preparations for UCIe and PCIe PHY interfaces. Alchip’s offerings encompass critical elements that are hard to find elsewhere, particularly proven 3DIC IP, indicating a significant technological advantage in a competitive market.
This 3DIC test chip achievement is especially significant as it demonstrates the technical validation of Alchip's ecosystem, reassuring developers and engineers working on AI and high-performance computing (HPC) projects. The robust ASIC ecosystem facilitates a swift time-to-design and provides a clear methodology for creating sophisticated ASIC devices, essential in today's rapidly evolving technological landscape.
The tape-out process represents an essential phase in chip development, particularly when working with the intricate components of a 3DIC setup, which differ markedly from traditional 2D chips. Alchip’s innovative design features a 3nm top die paired with a 5nm base die, which is fabricated using TSMC’s advanced SoIC-X packaging technology. This architecture allows significant insights into power density and thermal management challenges often associated with 3D chip integrations.
Within the chip, a powerful CPU and NPU core resides on the top die, while essential elements like a network-on-chip, L3 cache, and interface IP are housed in the base die. The connection between the two layers employs APLink-3D Lite IO technology, and the tape-out has successfully validated several crucial 3DIC functionalities, such as:
- Cross-die synchronous die-to-die IP integration.
- Design-for-test methodologies including redundancy and repair features.
- Thorough signal and power integrity assessments for 3D stacking.
- Thermal and mechanical simulations aiding vertical integration.
- Comprehensive implementation and verification of physical 3D designs.
According to Erez Shaizaf, CTO of Alchip, the successful tape-out is a testament to their advanced design flow and selected die-to-die IP, marking a pivotal milestone for the firm. In his words, "It’s a significant milestone that confirms our readiness," highlighting the importance of this achievement for the company.
The complex dual-die design necessitated a fresh approach to integrating physical and logical components. To facilitate co-design across both dies, EDA tools and methodologies were meticulously updated, ensuring a seamless sign-off process that includes thorough electrical, timing, and mechanical integrity checks across the entire 3D assembly.
Moreover, the company has rigorously tested Interface IP that has been specifically designed for 3DIC applications. This has indicated the pressing need for new IP due to the required interoperability and functional demands of 3D designs, especially where unique PHY implementations are crucial for protocols such as UCIe and PCIe.
A noteworthy advancement highlighted in this process is the development of 3DI/O timing, which has effectively managed to limit die-to-die latency to an impressive 40 picoseconds. This innovation enables efficient timing pathways that span across dies without compromising performance, with a fully integrated 3D clocking structure ensuring precise operation across both layers with minimal timing skew.
Involving multiple stakeholders, four IP vendors were part of the test chip program. Two vendors contributed proven hard macros while the others tested new IP on this pioneering platform. Additionally, a dedicated EDA flow vendor worked alongside Alchip to ensure that tools and methodologies were equipped for this innovative technology.
About Alchip Technologies
Founded in 2003 and based in Taipei, Alchip Technologies Ltd. is recognized globally as a prominent provider of ASICs for High-Performance Computing and AI infrastructures. The firm specializes in integrated circuit and packaging design and production services, catering specifically to the demands of companies developing sophisticated and high-volume ASICs and System on Chips (SoCs). Their commitment to delivering rapid time-to-market solutions ensures that clients leverage the best available technology, even in mainstream and advanced process settings. With a solid reputation built on state-of-the-art 2.5D/3D CoWoS packaging and meticulous chiplet design, Alchip serves a diverse range of industry leaders in sectors such as artificial intelligence, supercomputing, mobile communications, and more. Notably, Alchip Technologies is listed on the Taiwan Stock Exchange under the ticker TAI:3661.TW.
For further inquiries or additional information, please explore Alchip's official website.
Frequently Asked Questions
What is the significance of Alchip's 3DIC test chip?
The test chip validates Alchip’s integrated 3DIC solutions, enhancing its competitive edge in AI and HPC development.
What technologies are included in the 3DIC test chip?
The chip includes CPU/NPU core demonstrations, UCIe and PCIe PHY preparation, and critical third-party IP integrations.
How does the 3DIC chip design differ from traditional designs?
It features a layered structure where a 3nm die is integrated with a 5nm die, which poses unique thermal and power density challenges.
What advancements in IP technology were achieved?
New IP implementations were necessary to cater for the specific needs of 3D integrations, focusing on improved interoperability and functionality.
Who were the collaborators in the test chip program?
Four IP vendors participated, contributing both established and new technologies alongside an EDA flow vendor for tool readiness.
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