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Andes Technology Marks Two Decades with 2025 RISC-V CON Event

Andes Technology Marks Two Decades with 2025 RISC-V CON Event

Celebrating Two Decades of Innovation at RISC-V CON

Andes Technology, a prominent player in the RISC-V ecosystem, is gearing up for a remarkable event as it celebrates 20 years of innovation. The Silicon Valley 2025 Andes RISC-V CON is set to draw industry leaders, developers, and engineers interested in the exciting future of RISC-V technology.

Highlights of the Upcoming RISC-V CON

The event is scheduled to take place on April 29, offering an extensive lineup of sessions focusing on advancements in RISC-V. Participants will engage with Andes executives and well-known personalities from the tech sector, gaining insights into the latest breakthroughs and projects that are reshaping the RISC-V landscape.

Networking Opportunities for Attendees

A significant attraction of this year's conference is the chance for attendees to network. They will be able to connect with industry peers and partners, thus fostering a collaborative environment aimed at sharing knowledge and experience in RISC-V applications.

Conference Structure: Main Conference and Developer Track

The RISC-V CON will feature two distinct tracks: the Main Conference and the Developer Track. The Main Conference invites all participants, presenting over ten intriguing sessions that detail the RISC-V market and its application across various sectors, including AI, automotive, and communications. Meanwhile, the Developer Track is a dedicated space for engineers, providing intensive, hands-on training sessions.

Main Conference Insights and Key Presentations

The Main Conference will commence with key presentations from influential figures in the industry. Notable speakers include Frankwell Lin, Chairman and CEO of Andes Technology, who will reflect on two decades of continuous innovation, and Dr. Charlie Su, the company's President and CTO, who will share insights into advancing modern computing through RISC-V solutions.

Special Presentations on Cutting-Edge Technologies

Attendees can also look forward to special presentations about groundbreaking technologies. One such highlight is a discussion on Fully Homomorphic Encryption led by Paul Master from Cornami, presenting an exciting glimpse into the future of secure data processing.

A Fireside Chat and Industry Perspectives

Additional noteworthy sessions include a fireside chat exploring the next big shifts in AI, featuring experts like Jeff Bier and Pete Warden discussing future trends and innovations.

Developer Track: A Hands-On Experience

Engineers at the RISC-V CON will have the opportunity to participate in the Developer Track, which consists of four in-depth, hands-on sessions. This track is designed for those interested in optimizing and enhancing their experience with RISC-V technology.

Topics to Explore in the Developer Track

Some exciting topics covered in the Developer Track include RISC-V Vector ISA optimization for improved performance, advanced debugging with IAR tools, creating custom instructions for RISC-V, and techniques for optimizing heterogeneous computing resources.

Event Details and Registration Information

This year’s RISC-V CON will take place at the DoubleTree by Hilton in San Jose. Doors open at 8:30 AM and the event will wrap up at 6:00 PM PDT. Admission is free, and early registration is encouraged to secure seating at the popular Developer Track.

About Andes Technology

Andes Technology, recognized as a Founding Premier member of RISC-V International, is committed to driving the widespread adoption of RISC-V technology. The company has built an impressive portfolio ranging from ultra-efficient 32-bit CPUs to high-performance 64-bit systems. Their efforts have resulted in over 16 billion SoCs being deployed worldwide, advocating innovation across various sectors, including AI, automotive, and consumer electronics. To find out more about their innovative solutions, feel free to visit www.andestech.com.

Frequently Asked Questions

What is the RISC-V CON?

The RISC-V CON is an annual event organized by Andes Technology that highlights advancements in RISC-V technology and promotes networking amongst industry professionals.

Who can attend the RISC-V CON?

The event is open to all attendees, particularly targeting innovators, developers, and engineers involved in RISC-V technology.

What type of sessions will be available for developers?

The Developer Track will offer hands-on sessions including topics like RISC-V Vector ISA optimization, creating custom instructions, and resource optimization techniques.

Where will the event take place?

The RISC-V CON will be hosted at DoubleTree by Hilton in San Jose.

Is there a registration fee for attending the RISC-V CON?

No, the RISC-V CON is free to attend, but registration is recommended to ensure a place at the sessions.

About The Author

About Investors Hangout

Investors Hangout is a leading online stock forum for financial discussion and learning, offering a wide range of free tools and resources. It draws in traders of all levels, who exchange market knowledge, investigate trading tactics, and keep an eye on industry developments in real time. Featuring financial articles, stock message boards, quotes, charts, company profiles, and live news updates. Through cooperative learning and a wealth of informational resources, it helps users from novices creating their first portfolios to experts honing their techniques. Join Investors Hangout today: https://investorshangout.com/

The content of this article is based on factual, publicly available information and does not represent legal, financial, or investment advice. Investors Hangout does not offer financial advice, and the author is not a licensed financial advisor. Consult a qualified advisor before making any financial or investment decisions based on this article. This article should not be considered advice to purchase, sell, or hold any securities or other investments. If any of the material provided here is inaccurate, please contact us for corrections.

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