Advantest Rolls Out SiConic: A Quantum Leap in Silicon Validation
In a notable move for the semiconductor sector, Advantest Corporation (JPX: 6857) has officially introduced SiConic, which stands as a revolutionary solution designed to facilitate automated silicon validation. This new offering is particularly aimed at tackling the escalating complexity associated with advanced systems-on-chip (SoCs). It empowers design verification (DV) and silicon validation (SV) engineers by drastically improving sign-off times with exceptional reliability, effectiveness, and collaborative features.
Understanding the Semiconductor Landscape
Today’s semiconductor industry is rapidly evolving and encountering significant hurdles. The soaring complexity of SoC designs is paired with the increasing integration of 3D packaging and heterogeneous systems, which is stretching the limits of traditional validation processes. Teams focused on DV and SV are feeling a substantial push to expedite both market entry and quality assurance, particularly as the volume of devices featuring intricate functionalities continues to increase under tight deadlines.
Tackling Workflow Inefficiencies
To achieve breakthroughs in efficiency and quality, leveraging verification artifacts produced during the pre-silicon phase is crucial. Yet, the industry has been crippled by a lack of automated workflows and tools that could reliably extend verification procedures to silicon validation. SiConic seeks to eliminate this gap. By fostering strong collaborations with numerous EDA partners, including Cadence, Siemens, and Synopsys, SiConic enhances the capacity for engineering efficiency and accelerates the execution of real silicon tests.
Components of SiConic
At the heart of the SiConic solution lies SiConic Explorer, which functions as the software backbone. This platform establishes an automated flow through seamless integration with EDA verification tools founded on the Accellera Portable Test and Stimulus Standard (PSS). Notably, the Cadence Perspec System Verifier integrates effortlessly, enhancing the functionality of SiConic.
Hardware Innovations with SiConic Link
The physical hardware aspect, SiConic Link, introduces robust high-speed I/O (HSIO) capabilities and supports vital protocols like PCIe and USB. Its purpose is to facilitate functional validation at high throughput rates, combined with comprehensive tracing capabilities during the testing phases. Furthermore, this instrument grants control over interfaces such as JTAG and SPI, streamlining debuggers' workflows while allowing extensive monitoring of devices within their target environments.
Bridging Pre- and Post-Silicon Techniques
With the advent of SiConic, DV engineers can now utilize familiar pre-silicon methodologies to enhance their functional coverage in post-silicon scenarios. Conversely, SV engineers can load, configure parameters, and debug PSS-based or manually crafted content on silicon, ensuring swift and dependable device ramp-up and functional characterization. This portable solution is easily scalable, making it an ideal fit for distributed global R&D teams engaged in complex SoC projects featuring diversified IP blocks.
Fostering Collaboration and Building Trust
The capabilities of SiConic encourage informed sign-off decisions through increased team collaboration and insights backed by data. This not only cultivates trust with clients but also reassures them about the reliability of early sample deliveries and operations throughout the lifespan of their systems.
Community and Industry Engagement
The reception for SiConic among Advantest’s key clients in the IC space and EDA partners has been overwhelmingly positive, as they are already experiencing tangible performance and productivity benefits.
Industry leaders, like Alex Starr of AMD, emphasize the necessity for innovative pre- and post-silicon validation methods to meet quality standards, particularly amidst the shift towards multi-chiplet designs. Similarly, Cadence's Paul Cunningham outlines the critical need for solutions that address the complexities emerging from AI and automotive applications, expressing enthusiasm about the complementary nature of their verification technologies with the SiConic platform.
Showcasing SiConic at Major Events
Advantest is slated to dive deeper into the SiConic features at the upcoming DVCon, presenting insights during a tutorial hosted by Cadence and engaging in discussions about device sign-off with Qualcomm.
An Overview of Advantest Corporation
Established in 1954, Advantest (JPX: 6857) leads the globe in manufacturing automated test and measurement tools essential for semiconductor design and production. Its prowess extends across various demanding applications, including 5G communications, IoT, and AI. Advantest is dedicated to innovation, actively conducting research to overcome emerging testing challenges, creating solutions for wafer sorts, and contributing to sustainable practices globally.
Frequently Asked Questions
What is SiConic by Advantest?
SiConic is a groundbreaking solution designed to automate silicon validation, addressing the complexities of modern semiconductor testing.
How does SiConic improve semiconductor validation?
It enhances efficiency by allowing engineers to reuse pre-silicon verification techniques on silicon, simplifying and expediting the validation process.
Who are the key partners involved with SiConic?
Key partnerships include Cadence, Siemens, and Synopsys, helping to create a comprehensive ecosystem around SiConic.
What features does SiConic Link offer?
SiConic Link provides high-speed I/O support and enables functional validation with extensive control and observability during testing.
Where can I learn more about Advantest?
For additional information, you can visit Advantest's official website, which contains resources and insights into their complete portfolio.
